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1.发明授权Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories 失效杯芯片具有标签比较器和片上地址转换单元，并连接到片外高速缓存和主存储器
公开(公告)号：US4953073A
公开(公告)日：1990-08-28
申请号：US827269
申请日：1986-02-06
CPC分类号： G06F12/0848 , G06F12/1054
摘要： A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and tag busses.
摘要翻译： 基于缓存的计算机体系结构具有将地址生成单元和标签比较器封装在一起并与高速缓存RAMS分离。 如果架构支持虚拟存储器，地址转换单元可以包括在与地址生成单元和标签比较器逻辑之间的逻辑上相同的芯片上。 此外，可以在外部地址，数据和标签总线上实现对多于一个高速缓存的交织访问。
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2.发明授权System having an address generating unit and a log comparator packaged as an integrated circuit seperate from cache log memory and cache data memory 失效具有与缓存日志存储器和高速缓存数据存储器分离的集成电路的地址生成单元和对数比较器的系统
公开(公告)号：US5113506A
公开(公告)日：1992-05-12
申请号：US491114
申请日：1990-03-09
CPC分类号： G06F12/0848 , G06F12/1054
摘要： A cache-based computer architecture is disclosed in which the address generating unit and the tag comparator are packaged together and separately from the cache RAMs. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating unit and the tag comparator logic. Further, interleaved access to more than one cache may be accomplished on the external address, data and the tag busses.
摘要翻译： 公开了一种基于缓存的计算机架构，其中地址生成单元和标签比较器被封装在一起并与高速缓冲存储器RAM分开。 如果架构支持虚拟存储器，地址转换单元可以包括在与地址生成单元和标签比较器逻辑之间的逻辑上相同的芯片上。 此外，可以在外部地址，数据和标签总线上实现对多于一个高速缓存的交织访问。
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公开(公告)号：US4488228A
公开(公告)日：1984-12-11
申请号：US446801
申请日：1982-12-03
CPC分类号： G06F9/3863 , G06F11/141 , G06F9/3824
摘要： A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.
摘要翻译： 能够在指令执行期间检测到访问故障时能够自动地在外部存储器中存储与其内部状态相关的所有必要信息的数据处理器。 在纠正故障原因时，数据处理器根据检索的状态信息自动检索存储的状态信息并恢复其状态。 数据处理器然后恢复执行该指令。 可以在恢复指令执行时选择性地重新运行故障访问。 提供装置以验证所检索的状态信息是否有效。
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公开(公告)号：US4805098A
公开(公告)日：1989-02-14
申请号：US860304
申请日：1986-05-05
CPC分类号： G06F13/1631
摘要： Apparatus is disclosed for buffering writes from a CPU to main memory, in which sequential write requests to the same address are gathered and combined into a single write request. The embodiment described does not permit gathering with the write request in the buffer which is next scheduled for action by the main memory bus controller, nor does it permit gathering with other than the immediately preceding write request. The invention is implemented using a plurality of buffer ranks, each comprising a data rank, an address rank, and a valid rank for indicating which bits or bytes of the data rank contain data to be written to memory.
摘要翻译： 公开了用于缓冲从CPU到主存储器的写入的装置，其中对相同地址的顺序写入请求被收集并组合成单个写请求。 所描述的实施例不允许在下一次由主存储器总线控制器执行动作的缓冲器中的写入请求进行采集，也不允许与紧接在前的写入请求之外的采集。 本发明使用多个缓冲器级别实现，每个缓冲器级别包括数据等级，地址级别和有效等级，用于指示数据等级的哪些位或字节包含要写入存储器的数据。
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公开(公告)号：US4633437A
公开(公告)日：1986-12-30
申请号：US624660
申请日：1984-06-26
CPC分类号： G06F13/387 , G06F13/4018
摘要： In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.
摘要翻译： 在适于对给定尺寸的操作数执行操作的数据处理器中，提供总线控制器以将操作数与具有可能是操作数大小的数字端口的存储设备通信。 响应于来自总线控制器的请求传送特定大小的操作数的信号，存储设备提供指示可用于容纳所请求传送的数据端口的大小的大小信号。 根据要传输的操作数的大小和存储设备的数据端口的大小，总线控制器可能会将操作数传输周期中断到几个总线周期，以便完全传输操作数。 在此过程中，总线控制器补偿操作数与数据端口之间的任何地址不对齐。 为了区分各个操作数周期与可能包括操作数周期的几个总线周期，总线控制器仅在每个操作数周期的第一个总线周期开始时提供操作数周期开始信号。
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公开(公告)号：US4349873A
公开(公告)日：1982-09-14
申请号：US136593
申请日：1980-04-02
CPC分类号： G06F9/4812 , G06F11/0721 , G06F11/0745 , G06F11/0751 , G06F11/0757
摘要： An integrated circuit data processor receives interrupt level signals from external circuitry which represent a priority level associated with the external circuitry. These signals are compared with signals representing the current operating level of the processor, and an interrupt pending output is generated if (1) the priority level is higher than the operating level; or (2) a maximum priority level is received. Upon the occurrence of the interrupt pending output, the current instruction program is interrupted, and an instruction program associated with the external circuitry is executed. The processor transmits a signal back to the external circuitry indicating that the interrupt request has been granted and receives a vector number from the external circuitry. A first acknowledgment signal from the external circuitry causes the vector number to be latched in the processor. A second acknowledgment signal from the external circuitry causes a vector to be internally generated. Error circuitry is provided to detect spurious interrupts.
摘要翻译： 集成电路数据处理器从外部电路接收表示与外部电路相关联的优先级的中断电平信号。 将这些信号与表示处理器的当前操作电平的信号进行比较，并且如果（1）优先级高于操作电平，则产生中断等待输出; 或（2）接收到最大优先级。 当发生中断等待输出时，当前指令程序中断，并且执行与外部电路相关联的指令程序。 处理器向外部电路发送一个信号，指示中断请求已被授权，并从外部电路接收一个向量号。 来自外部电路的第一确认信号使得矢量编号被锁存在处理器中。 来自外部电路的第二确认信号导致向量在内部产生。 提供错误电路来检测虚假中断。
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公开(公告)号：US4757445A
公开(公告)日：1988-07-12
申请号：US79191
申请日：1987-07-29
CPC分类号： G06F9/30149 , G06F9/3816 , G06F9/3865
摘要： A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.
摘要翻译： 一种用于验证预取指令的方法和数据处理系统。 该系统包括指令单元，n级流水线，其提供表示从存储器到指令单元的指令字的数据段。 该系统还包括用于预取在当前执行的指令之后执行的指令字的电路，以及用于在执行单元执行之前验证预取指令字的有效性的电路，以及用于使指令单元 故障条件只有当无效指令的执行开始时。
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8.发明授权
公开(公告)号：US4947357A
公开(公告)日：1990-08-07
申请号：US159898
申请日：1988-02-24
IPC分类号： G01R31/3185
CPC分类号： G01R31/318558
摘要： A digital system that includes a plurality of integrated circuits disposed on a circuit board, each integrated circuit comprising a plurality of scan chains, each scan chain scanning data from a scan input to a scan output in response to a scan clock; each scan input is coupled to a first pad of the integrated circuit, and the scan outputs are multiplexed to a second pad of the integrated circuit; the second pads of the integrated circuits are multiplexed to a port of the circuit board. A controller selects one of the integrated circuits for scanning, the controller selecting the second pad of the selected integrated circuit for coupling to the port of the circuit board; and the controller also selects one of the plurality of scan chains in the selected integrated circuit for scanning, the controller coupling the scan clock to the selected scan chain and selecting the scan output of the selected scan chain for coupling to the second pad of the selected integrated circuit.
摘要翻译： 一种数字系统，包括设置在电路板上的多个集成电路，每个集成电路包括多个扫描链，每个扫描链扫描数据从扫描输入到响应于扫描时钟的扫描输出; 每个扫描输入耦合到集成电路的第一焊盘，并且扫描输出被复用到集成电路的第二焊盘; 集成电路的第二焊盘被复用到电路板的端口。 控制器选择用于扫描的集成电路中的一个，控制器选择所选择的集成电路的第二焊盘以耦合到电路板的端口; 并且所述控制器还选择所选择的集成电路中的所述多个扫描链中的一个进行扫描，所述控制器将所述扫描时钟耦合到所选择的扫描链，并且选择所选择的扫描链的扫描输出以耦合到所选择的扫描链的第二焊盘 集成电路。
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公开(公告)号：US4710866A
公开(公告)日：1987-12-01
申请号：US930941
申请日：1986-10-07
CPC分类号： G06F9/3865 , G06F9/3802
摘要： A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.
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公开(公告)号：US4348722A
公开(公告)日：1982-09-07
申请号：US136845
申请日：1980-04-03
CPC分类号： G06F11/141
摘要： An integrated circuit microprocessor includes storage means coupled to a control unit for receiving from the control unit information regarding how the next bus cycle is to be run. Upon receipt of a bus error signal from a peripheral device, the storage means is reset. If, however, a halt signal accompanies the bus error signal, the storage means is not reset and the bus cycle is rerun when the halt signal terminates.
摘要翻译： 集成电路微处理器包括耦合到控制单元的存储装置，用于从控制单元接收关于如何运行下一个总线周期的信息。 在从外围设备接收到总线错误信号时，存储装置被复位。 然而，如果停止信号伴随总线误差信号，则存储装置不复位，并且当停止信号终止时总线周期重新运行。
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