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    Method and apparatus for validating prefetched instruction
    2.
    发明授权
    Method and apparatus for validating prefetched instruction 失效
    用于验证预取指令的方法和装置

    公开(公告)号：US4757445A

    公开(公告)日：1988-07-12

    申请号：US79191

    申请日：1987-07-29

    申请人： John Zolnowsky ,  Lester M. Crudele ,  Michael E. Spak

    发明人： John Zolnowsky ,  Lester M. Crudele ,  Michael E. Spak

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F11/00

    CPC分类号： G06F9/30149 ,  G06F9/3816 ,  G06F9/3865

    摘要： A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.

    摘要翻译： 一种用于验证预取指令的方法和数据处理系统。 该系统包括指令单元，n级流水线，其提供表示从存储器到指令单元的指令字的数据段。 该系统还包括用于预取在当前执行的指令之后执行的指令字的电路，以及用于在执行单元执行之前验证预取指令字的有效性的电路，以及用于使指令单元 故障条件只有当无效指令的执行开始时。

    Keypad scanner
    3.
    发明授权
    Keypad scanner 失效
    键盘扫描仪

    公开(公告)号：US5621402A

    公开(公告)日：1997-04-15

    申请号：US95923

    申请日：1993-07-21

    申请人： Michael E. Spak ,  Dale E. Gulick

    发明人： Michael E. Spak ,  Dale E. Gulick

    IPC分类号： G06F3/02 ,  G06F3/023 ,  H03M11/20 ,  H03K17/94

    CPC分类号： H03M11/20

    摘要： A keypad scanner for a keypad having a plurality of keys which may be pressed into a down state includes circuitry for detecting when no or any key is pressed down and thereupon generating a no or any key down signal, circuitry for detecting when more than one key is pressed down and thereupon generating a multiple key down signal, and an interrupt generator coupled to the aforementioned circuitry. The interrupt generator itself includes circuitry for detecting a change in no or any key down signal level, circuitry for detecting a change in multiple key down signal level, and circuitry for generating an interrupt signal when either the circuitry for detecting a change in no or any key down signal level or the circuitry for detecting a change in multiple key down signal level detects a change.

    摘要翻译： 用于具有可以被按压到下降状态的多个键的小键盘的键盘扫描器包括用于检测什么时候没有或任何键被按下并且随后产生无或任何键降低信号的电路，用于检测何时多于一个键 被按下并随后产生多重按键信号，以及耦合到上述电路的中断发生器。 中断发生器本身包括用于检测无或任何按键降低信号电平变化的电路，用于检测多个键下降信号电平变化的电路，以及用于当用于检测否或任何信号的改变的电路时产生中断信号的电路 键下降信号电平或用于检测多重键下降信号电平变化的电路检测到变化。

    Configurable digital wireless and wired communications system architecture for implementing baseband functionality
    5.
    发明授权
    Configurable digital wireless and wired communications system architecture for implementing baseband functionality 失效
    可配置的数字无线和有线通信系统架构，用于实现基带功能

    公开(公告)号：US5790817A

    公开(公告)日：1998-08-04

    申请号：US719799

    申请日：1996-09-25

    申请人： Saf M. Asghar ,  Michael E. Spak

    发明人： Saf M. Asghar ,  Michael E. Spak

    IPC分类号： H04B1/16 ,  H04B1/30 ,  H04B1/40 ,  H04W88/02 ,  H01J13/00

    CPC分类号： H04W88/02 ,  H04B1/0003 ,  H04B1/406 ,  H04B1/16 ,  H04B1/30 ,  Y02B60/50

    摘要： A configurable multiprocessor communications architecture which performs digital communications functions and which is configurable for different digital communications standards, such as various digital cellular standards. In the preferred embodiment, the multiprocessor architecture includes two or more digital signal processing cores, a microcontroller or micro-scheduler, a voice coder/decoder (codec), and a relatively low performance central processing unit (CPU). Each of the above devices are coupled to a system memory. The general purpose CPU preferably performs user interface functions and overall communications management functions. A CPU local memory and various peripheral devices are coupled through a CPU local bus to the CPU, and these devices are accessible to the CPU without the CPU having to access the main system bus. A dual port bus arbiter is preferably coupled between the CPU and the system bus and controls access to the system bus and the CPU local bus. The micro-scheduler operates to schedule operations and/or functions, as well as dynamically control the clock rates, of each of the DSPs and the hardware acceleration logic to achieve the desired throughput while minimizing power consumption. The present invention thus provides a single architecture which has simplified configurability for different digital standards. The configurable digital communications architecture simplifies design and manufacturing costs and provides improved performance over prior designs.

    摘要翻译： 一种可配置的多处理器通信架构，其执行数字通信功能并且可配置用于不同数字通信标准，例如各种数字蜂窝标准。 在优选实施例中，多处理器架构包括两个或多个数字信号处理核心，微控制器或微调度器，语音编码器/解码器（编解码器）和相对低性能的中央处理单元（CPU）。 上述每个设备耦合到系统存储器。 通用CPU优选地执行用户界面功能和整体通信管理功能。 CPU本地存储器和各种外围设备通过CPU本地总线耦合到CPU，并且CPU可访问这些设备，而CPU不必访问主系统总线。 双端口总线仲裁器优选地耦合在CPU和系统总线之间，并控制对系统总线和CPU本地总线的访问。 微调度器操作以调度操作和/或功能，以及动态地控制每个DSP和硬件加速度逻辑的时钟速率，以实现期望的吞吐量同时最小化功耗。 因此，本发明提供了一种具有简化的用于不同数字标准的可配置性的单一架构。 可配置的数字通信架构简化了设计和制造成本，并提供了比以前的设计更好的性能。

    A Ram cell having means for controlling a bidirectional shift
    6.
    发明授权
    A Ram cell having means for controlling a bidirectional shift 失效
    具有用于控制双向移位的装置的Ram单元

    公开(公告)号：US4864544A

    公开(公告)日：1989-09-05

    申请号：US272563

    申请日：1988-11-17

    申请人： Michael E. Spak ,  Craig S. Tyl ,  Philip C. Wottrich

    发明人： Michael E. Spak ,  Craig S. Tyl ,  Philip C. Wottrich

    IPC分类号： G06F7/78 ,  G11C11/412 ,  G11C19/00 ,  G11C19/28

    CPC分类号： G06F7/78 ,  G11C11/412 ,  G11C19/00 ,  G11C19/28

    摘要： A memory cell is comprised of a cross-coupled master latch and a cross-coupled slave latch. The memory cell includes means for switching on and off power supplies connected to the master latch and the slave latch so as to control the direction of shift in a bidirectional shift. Data is shifted in a first direction when the power supply connected to the master latch is switched off, and data is shifted in a second direction when the power supply connected to the slave latch is switched off.

    摘要翻译： 存储器单元由交叉耦合主锁存器和交叉耦合从锁存器组成。 存储单元包括用于接通和断开连接到主锁存器和从锁存器的电源的装置，以便控制双向移位中的移位方向。 当连接到主​​锁存器的电源被关闭时，数据沿着第一方向移位，并且当连接到从锁存器的电源被关闭时，数据沿第二方向移位。

    Fracturable x-y storage array using a ram cell with bidirectional shift
    7.
    发明授权
    Fracturable x-y storage array using a ram cell with bidirectional shift 失效
    使用具有双向移位的柱塞单元的可破碎的x-y存储阵列

    公开(公告)号：US4813015A

    公开(公告)日：1989-03-14

    申请号：US838993

    申请日：1986-03-12

    申请人： Michael E. Spak ,  Craig S. Tyl ,  Philip C. Wottrich

    发明人： Michael E. Spak ,  Craig S. Tyl ,  Philip C. Wottrich

    IPC分类号： G11C7/00 ,  G06F7/78 ,  G11C11/412 ,  G11C19/00 ,  G11C19/28 ,  G11C8/00

    CPC分类号： G06F7/78 ,  G11C11/412 ,  G11C19/00 ,  G11C19/28

    摘要： A fracturable x-y random access memory array for performing pushing and popping of data and fracturing the array simultaneously at a common address includes a row fracture circuit responsive to row addresses to fracture the array in the Y-direction and a column fracture circuit responsive to column addresses for fracturing the array in the X-direction. A plurality of memory cells are stacked in a plurality of columns to form an x-y organization which can be randomly accessed in response to the row and column addresses. The memory cells are responsive to a shift control driver circuit for bidirectional shifting of data by either pushing data into or popping data from at any point within one of the plurality of randomly addressable column at the same row and column addresses used to fracture the array defining a fracture point. Data in all of the memory cells in the array with addresses higher (or lower) than the fracture point shift and the memory cells with addresses lower (or higher) than the fracture point maintain their data unchanged.

    摘要翻译： 用于执行数据的推动和弹出并且以公共地址同时压裂阵列的可分裂的xy随机存取存储器阵列包括响应于行地址的行断裂电路来使阵列在Y方向上断裂，以及响应于列地址的列断裂电路 用于在X方向上压裂阵列。 多个存储器单元被堆叠在多个列中以形成可以响应于行和列地址而被随机访问的x-y组织。 存储器单元响应于移位控制驱动器电路，用于通过将数据从与多个可随机寻址列中的一个内的任何点处的数据推入或弹出数据进行双向移位，所述相同行和列地址用于破坏定义的数组 骨折点。 阵列中的所有存储单元中的数据，其地址比断裂点位移更高（或更低），并且具有比断裂点更低（或更高）的地址的存储单元保持其数据不变。

    ALU and Condition code control unit for data processor
    8.
    发明授权
    ALU and Condition code control unit for data processor 失效
    ALU和数据处理器的条件代码控制单元

    公开(公告)号：US4312034A

    公开(公告)日：1982-01-19

    申请号：US41203

    申请日：1979-05-21

    申请人： Thomas G. Gunter ,  Colleen M. E. Hobbs ,  Michael E. Spak ,  Harry L. Tredennick

    发明人： Thomas G. Gunter ,  Colleen M. E. Hobbs ,  Michael E. Spak ,  Harry L. Tredennick

    IPC分类号： G06F9/26 ,  G06F9/30 ,  G06F9/32

    CPC分类号： G06F9/30094 ,  G06F9/262 ,  G06F9/30145 ,  G06F9/30167

    摘要： A data processor which is adapted for microprogrammed operation has a control store includes an ALU and condition code control unit for controlling operations performed by an arithmetic-logic unit within the execution unit of the data processor and for controlling the setting of the condition code bits in a status register. The ALU and condition code control unit is arranged in a row and column format. A decoder coupled to a macroinstruction register selects a row which is selected over an entire period that is required to execute macroinstruction. The row corresponds to a set of operations and condition code settings associated with a particular macroinstruction. The control store output provides information for selecting the proper column during each microcycle used to execute the macroinstruction. ALU function control signals and the condition code control signals are selected simultaneously according to the selected row and column.

    摘要翻译： 适用于微程序操作的数据处理器具有控制存储器，其包括ALU和条件代码控制单元，用于控制由数据处理器的执行单元内的算术逻辑单元执行的操作，并用于控制数据处理器中的条件码位的设置 状态寄存器。 ALU和条件代码控制单元以行和列格式排列。 耦合到宏指令寄存器的解码器选择在执行宏指令所需的整个周期中选择的行。 该行对应于与特定宏指令相关联的一组操作和条件代码设置。 控制存储输出提供用于在用于执行宏指令的每个微循环期间选择适当列的信息。 ALU功能控制信号和条件代码控制信号根据所选行和列同时选择。