公开(公告)号：US20240290382A1

公开(公告)日：2024-08-29

申请号：US18658819

申请日：2024-05-08

Applicant: KIOXIA CORPORATION

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Toshifumi HASHIMOTO

IPC: G11C11/56 ,  G11C5/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C11/5642 ,  G11C5/14 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

公开(公告)号：US20250022512A1

公开(公告)日：2025-01-16

申请号：US18899645

申请日：2024-09-27

Applicant: Kioxia Corporation

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Shuhei OKETA ,  Mai SHIMIZU

IPC: G11C16/08 ,  G11C16/04

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

公开(公告)号：US20220319590A1

公开(公告)日：2022-10-06

申请号：US17846889

申请日：2022-06-22

Applicant: KIOXIA CORPORATION

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Toshifumi HASHIMOTO

IPC: G11C11/56 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

公开(公告)号：US20230307051A1

公开(公告)日：2023-09-28

申请号：US17897089

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Shuhei OKETA ,  Mai SHIMIZU

IPC: G11C16/08 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

公开(公告)号：US20220084586A1

公开(公告)日：2022-03-17

申请号：US17184986

申请日：2021-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Toshifumi HASHIMOTO

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.