公开(公告)号：US20250022512A1

公开(公告)日：2025-01-16

申请号：US18899645

申请日：2024-09-27

Applicant: Kioxia Corporation

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Shuhei OKETA ,  Mai SHIMIZU

IPC: G11C16/08 ,  G11C16/04

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

公开(公告)号：US20230352099A1

公开(公告)日：2023-11-02

申请号：US18184893

申请日：2023-03-16

Applicant: KIOXIA CORPORATION

Inventor： Koji KATO ,  Yuki SHIMIZU ,  Shuhei OKETA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  H01L23/528 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C5/06

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  H01L23/5283 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C5/06

Abstract: A semiconductor memory device includes: conductive layers including a first range and a second range; a first semiconductor layer opposed to the conductive layers in the first range; a second semiconductor layer opposed to the conductive layers in the second range; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. When a sense time of the first bit line when a predetermined operation is performed on a first memory cell including a first electric charge accumulating portion is assumed to be a first operation parameter and a sense time of the second bit line when the predetermined operation is performed on a second memory cell including a second electric charge accumulating portion is assumed to be a second operation parameter, the second operation parameter differs from the first operation parameter.

公开(公告)号：US20230307051A1

公开(公告)日：2023-09-28

申请号：US17897089

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Shuhei OKETA ,  Mai SHIMIZU

IPC: G11C16/08 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.