公开(公告)号：US20240021251A1

公开(公告)日：2024-01-18

申请号：US18476477

申请日：2023-09-28

Applicant: KIOXIA CORPORATION

Inventor： Koji KATO

IPC: G11C16/26 ,  G11C16/32 ,  G11C16/10 ,  G11C16/24 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/32 ,  G11C16/10 ,  G11C16/24 ,  G11C16/0483 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.

公开(公告)号：US20230352099A1

公开(公告)日：2023-11-02

申请号：US18184893

申请日：2023-03-16

Applicant: KIOXIA CORPORATION

Inventor： Koji KATO ,  Yuki SHIMIZU ,  Shuhei OKETA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  H01L23/528 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C5/06

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  H01L23/5283 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C5/06

Abstract: A semiconductor memory device includes: conductive layers including a first range and a second range; a first semiconductor layer opposed to the conductive layers in the first range; a second semiconductor layer opposed to the conductive layers in the second range; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. When a sense time of the first bit line when a predetermined operation is performed on a first memory cell including a first electric charge accumulating portion is assumed to be a first operation parameter and a sense time of the second bit line when the predetermined operation is performed on a second memory cell including a second electric charge accumulating portion is assumed to be a second operation parameter, the second operation parameter differs from the first operation parameter.

公开(公告)号：US20230154547A1

公开(公告)日：2023-05-18

申请号：US18156654

申请日：2023-01-19

Applicant: KIOXIA CORPORATION

Inventor： Takeshi HIOKA ,  Tsukasa KOBAYASHI ,  Koji KATO ,  Yuki SHIMIZU ,  Hiroshi MAEJIMA

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  H10B43/27 ,  H10B43/30

CPC classification number: G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  H10B43/27 ,  H10B43/30

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

公开(公告)号：US20240290382A1

公开(公告)日：2024-08-29

申请号：US18658819

申请日：2024-05-08

Applicant: KIOXIA CORPORATION

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Toshifumi HASHIMOTO

IPC: G11C11/56 ,  G11C5/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C11/5642 ,  G11C5/14 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

公开(公告)号：US20240038305A1

公开(公告)日：2024-02-01

申请号：US18485630

申请日：2023-10-12

Applicant: Kioxia Corporation

Inventor： Mai SHIMIZU ,  Koji KATO ,  Yoshihiko KAMATA ,  Mario SAKO

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/0483 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/32 ,  G11C16/3427

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US20230178152A1

公开(公告)日：2023-06-08

申请号：US18161274

申请日：2023-01-30

Applicant: Kioxia Corporation

Inventor： Mai SHIMIZU ,  Koji KATO ,  Yoshihiko KAMATA ,  Mario SAKO

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/08 ,  G11C11/5642 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/0483 ,  G11C16/3427

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US20220366966A1

公开(公告)日：2022-11-17

申请号：US17645814

申请日：2021-12-23

Applicant: KIOXIA CORPORATION

Inventor： Koji KATO

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4076 ,  G11C5/06

Abstract: A semiconductor memory device includes a memory string, first wirings electrically connected to the memory string, second wirings electrically connected to the first wirings, transistors electrically connected between the first wirings and the second wirings, and a third wiring connected to gate electrodes of the transistors in common. The memory string includes memory transistors connected in series. Gate electrodes of the memory transistors are connected to the first wirings. The semiconductor memory device executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. A first voltage that turns the transistors ON is applied to the third wiring from an end of the first read operation to a start of the second read operation.

公开(公告)号：US20220238164A1

公开(公告)日：2022-07-28

申请号：US17473293

申请日：2021-09-13

Applicant: Kioxia Corporation

Inventor： Koji KATO

IPC: G11C16/26 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32

Abstract: A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.

公开(公告)号：US20210383868A1

公开(公告)日：2021-12-09

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki SHIMIZU ,  Yoshihiko KAMATA ,  Tsukasa KOBAYASHI ,  Hideyuki KATAOKA ,  Koji KATO ,  Takumi FUJIMOTO ,  Yoshinao SUZUKI ,  Yuui SHIMIZU

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US20240420765A1

公开(公告)日：2024-12-19

申请号：US18818527

申请日：2024-08-28

Applicant: Kioxia Corporation

Inventor： Mai SHIMIZU ,  Koji KATO ,  Yoshihiko KAMATA ,  Mario SAKO

IPC: G11C16/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.