公开(公告)号：US20220084586A1

公开(公告)日：2022-03-17

申请号：US17184986

申请日：2021-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Toshifumi HASHIMOTO

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

公开(公告)号：US20240290382A1

公开(公告)日：2024-08-29

申请号：US18658819

申请日：2024-05-08

Applicant: KIOXIA CORPORATION

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Toshifumi HASHIMOTO

IPC: G11C11/56 ,  G11C5/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C11/5642 ,  G11C5/14 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

公开(公告)号：US20240081065A1

公开(公告)日：2024-03-07

申请号：US18503233

申请日：2023-11-07

Applicant: KIOXIA CORPORATION

Inventor： Toshifumi HASHIMOTO

IPC: H10B43/27 ,  H01L23/00 ,  H01L29/792 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L24/46 ,  H01L29/792 ,  H10B43/10

Abstract: A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers, a first semiconductor column, a first electric charge accumulating film, a first wiring disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers and the second conductive layer, a first contact that is disposed between one end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring, and a second contact that is disposed between another end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring.

公开(公告)号：US20210343644A1

公开(公告)日：2021-11-04

申请号：US17159426

申请日：2021-01-27

Applicant: Kioxia Corporation

Inventor： Toshifumi HASHIMOTO ,  Jumpei SATO

IPC: H01L23/528 ,  H01L27/11573 ,  H01L23/532 ,  H01L23/522 ,  H01L27/1157

Abstract: A semiconductor memory device includes a semiconductor substrate, memory blocks, a first wiring, a second wiring, a first contact, a first transistor, and a second transistor. The memory blocks are spaced from the semiconductor substrate in a first direction and are arranged in a second direction. The first wiring is farther from the semiconductor substrate than the memory blocks. The second wiring is closer to the semiconductor substrate than the memory blocks. The first contact is electrically connected between the first wiring and the second wiring. The first and second transistors are disposed on the semiconductor substrate. The first transistor is electrically connected between the second wiring and a first memory block. The second transistor is electrically connected between the second wiring and a second memory block. The first contact is disposed between the first transistor and the second transistor in the second direction.

公开(公告)号：US20250054524A1

公开(公告)日：2025-02-13

申请号：US18921736

申请日：2024-10-21

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA ,  Toshifumi HASHIMOTO

IPC: G11C7/10 ,  G11C7/08 ,  G11C16/16

Abstract: A first conductor extends along first and second axes. A first memory pillar is provided in the first conductor and includes a first semiconductor and a charge accumulation layer. A second conductor extends along the second axis and is in contact with the first memory pillar. A third conductor extends along the first and second axes and is arranged with a distance from the first conductor along the second axis. A second memory pillar is provided in the third conductor and includes a second semiconductor and a charge accumulation layer. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is coupled to the first and second memory pillars.

公开(公告)号：US20240099031A1

公开(公告)日：2024-03-21

申请号：US18323528

申请日：2023-05-25

Applicant: KIOXIA CORPORATION

Inventor： Toshifumi HASHIMOTO

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory plane region includes a first structure and a second structure having conductive layers, and includes a first memory region to a third memory region, a first region between the first memory region and the second memory region, and a second region between the second memory region and the third memory region. The first structure comprises first via contact electrodes in the first region. The second structure comprises second via contact electrodes in the second region. The first via contact electrodes are electrically connected to transistors provided at positions where the first structure and the first region overlap, and where the second structure and the first region overlap. The second via contact electrodes are electrically connected to transistors provided at positions where the first structure and the second region overlap, and where the second structure and the second region overlap.

公开(公告)号：US20200051622A1

公开(公告)日：2020-02-13

申请号：US16654771

申请日：2019-10-16

Applicant: KIOXIA Corporation

Inventor： Weihan WANG ,  Toshifumi HASHIMOTO ,  Noboru SHIBATA

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/32 ,  G06F3/06 ,  G11C16/04

Abstract: A semiconductor memory device includes a first memory cell array including a first memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a second memory cell array including a second memory cell that is capable of holding two or more bits of data including at least a first bit and a second bit, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell. In a read operation, at least first, second, and third voltages are applied successively to both the first word line and the second word line to read a first page including the first bit of the first memory cell and a second page including the second bit of the second memory cell.

公开(公告)号：US20230074030A1

公开(公告)日：2023-03-09

申请号：US17984959

申请日：2022-11-10

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi MAEJIMA ,  Toshifumi HASHIMOTO ,  Takashi MAEDA ,  Masumi SAITOH ,  Tetsuaki UTSUMI

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

公开(公告)号：US20220319590A1

公开(公告)日：2022-10-06

申请号：US17846889

申请日：2022-06-22

Applicant: KIOXIA CORPORATION

Inventor： Tomoki NAKAGAWA ,  Koji KATO ,  Toshifumi HASHIMOTO

IPC: G11C11/56 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

公开(公告)号：US20210065771A1

公开(公告)日：2021-03-04

申请号：US16812944

申请日：2020-03-09

Applicant: KIOXIA CORPORATION

Inventor： Toshifumi HASHIMOTO

IPC: G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C16/26 ,  G11C16/34

Abstract: According to one embodiment, a memory system includes: a semiconductor memory including a memory cell array, the memory cell array including a memory cell, and a controller configured to issue a first read command sequence after a lapse of a first time period from access to the semiconductor memory, and issue a second read command sequence after a lapse of a second time period from access to the semiconductor memory. When the controller issues the first read command sequence, the semiconductor memory applies a first voltage and a second voltage to the memory cell. When the controller issues the second read command sequence, the semiconductor memory applies a third voltage and a fourth voltage to the memory cell.