公开(公告)号：US20080122030A1

公开(公告)日：2008-05-29

申请号：US11468472

申请日：2006-08-30

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

IPC分类号： H01L29/86 ,  H01L21/441

CPC分类号： H01L29/945 ,  H01L28/84 ,  H01L29/66181

摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

摘要翻译： 公开了用于增强沟槽电容的方法和如此形成的沟槽电容器。 在一个实施例中，一种方法包括形成沟槽的第一部分; 在所述第一部分中沉积介电层; 执行包括第一阶段的反应离子蚀刻以蚀刻所述电介质层并在所述沟槽的第一部分的底表面上形成微掩模，以及形成具有粗糙侧壁的所述沟槽的第二部分; 沉积节点电介质; 并用导体填充沟槽。 粗糙的侧壁增加沟槽电容，而不增加处理复杂性或成本。

公开(公告)号：US07560360B2

公开(公告)日：2009-07-14

申请号：US11468472

申请日：2006-08-30

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

IPC分类号： H01L21/20

CPC分类号： H01L29/945 ,  H01L28/84 ,  H01L29/66181

摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

摘要翻译： 公开了用于增强沟槽电容的方法和如此形成的沟槽电容器。 在一个实施例中，一种方法包括形成沟槽的第一部分; 在第一部分中沉积介电层; 执行包括第一阶段的反应离子蚀刻以蚀刻所述电介质层并在所述沟槽的第一部分的底表面上形成微掩模，以及形成具有粗糙侧壁的所述沟槽的第二部分; 沉积节点电介质; 并用导体填充沟槽。 粗糙的侧壁增加沟槽电容，而不增加处理复杂性或成本。

公开(公告)号：US20080248625A1

公开(公告)日：2008-10-09

申请号：US12120535

申请日：2008-05-14

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

IPC分类号： H01L21/441

CPC分类号： H01L29/945 ,  H01L28/84 ,  H01L29/66181

摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

公开(公告)号：US08426268B2

公开(公告)日：2013-04-23

申请号：US12698293

申请日：2010-02-02

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Byeong Y. Kim ,  Munir D. Naeem

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Byeong Y. Kim ,  Munir D. Naeem

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/66181

摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。 该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。 沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。 然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。 然后蚀刻层状半导体结构。 图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。 通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。

公开(公告)号：US08003488B2

公开(公告)日：2011-08-23

申请号：US11861614

申请日：2007-09-26

申请人： Kangguo Cheng ,  Munir D. Naeem ,  David M. Dobuzinsky ,  Byeong Y. Kim

发明人： Kangguo Cheng ,  Munir D. Naeem ,  David M. Dobuzinsky ,  Byeong Y. Kim

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L27/1087 ,  H01L21/84 ,  H01L27/1203

摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.

摘要翻译： 在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。 在深沟槽中形成导电沟槽填充区域。 施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。 具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。 对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。 去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。 另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。

公开(公告)号：US20090079027A1

公开(公告)日：2009-03-26

申请号：US11861614

申请日：2007-09-26

申请人： Kangguo Cheng ,  Munir D. Naeem ,  David M. Dobuzinsky ,  Byeong Y. Kim

发明人： Kangguo Cheng ,  Munir D. Naeem ,  David M. Dobuzinsky ,  Byeong Y. Kim

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L27/1087 ,  H01L21/84 ,  H01L27/1203

摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.

摘要翻译： 在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。 在深沟槽中形成导电沟槽填充区域。 施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。 具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。 对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。 去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。 另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。

公开(公告)号：US20100193852A1

公开(公告)日：2010-08-05

申请号：US12698293

申请日：2010-02-02

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Byeong Y. Kim ,  Munir D. Naeem

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Byeong Y. Kim ,  Munir D. Naeem

IPC分类号： H01L27/108 ,  H01L21/8242 ,  G06F17/50

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/66181

摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。 该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。 沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。 然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。 然后蚀刻层状半导体结构。 图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。 通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。

公开(公告)号：US20090189242A1

公开(公告)日：2009-07-30

申请号：US12020887

申请日：2008-01-28

申请人： Gregory Costrini ,  David M. Dobuzinsky ,  Thomas S. Kanarsky ,  Munir D. Naeem ,  Christopher D. Sheraw ,  Richard Wise

发明人： Gregory Costrini ,  David M. Dobuzinsky ,  Thomas S. Kanarsky ,  Munir D. Naeem ,  Christopher D. Sheraw ,  Richard Wise

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L29/045 ,  H01L21/76224

摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.

摘要翻译： 公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向 和具有第二结晶取向的体区。 使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个 材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。 可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。

公开(公告)号：US07514323B2

公开(公告)日：2009-04-07

申请号：US11164513

申请日：2005-11-28

申请人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

发明人： David M. Dobuzinsky ,  Herbert L. Ho ,  Jack A. Mandelman ,  Yoichi Otani

IPC分类号： H01L29/00

CPC分类号： H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.

摘要翻译： 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。

公开(公告)号：US06656375B1

公开(公告)日：2003-12-02

申请号：US09014806

申请日：1998-01-28

申请人： Michael D. Armacost ,  David M. Dobuzinsky ,  John C. Malinowski ,  Hung Y. Ng ,  Richard S. Wise ,  Chienfan Yu

发明人： Michael D. Armacost ,  David M. Dobuzinsky ,  John C. Malinowski ,  Hung Y. Ng ,  Richard S. Wise ,  Chienfan Yu

IPC分类号： C23F100

CPC分类号： H01L21/31116

摘要： An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH3F or CH2F2, the carbon source is preferably one of CO2 or CO, and the oxidant is preferably O2. The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.

摘要翻译： 用于衬底的氮化物层的各向异性蚀刻工艺，该方法包括使用包含富氢氟代烃，氧化剂和碳源的蚀刻剂气体。 富氢氟烃优选为CH 3 F或CH 2 F 2之一，碳源优选为CO 2或CO之一，氧化剂优选为O 2。 氟烃优选以约7％-35体积％存在于气体中，氧化剂优选以约1％-35％体积的比例存在于气体中，并且碳源优选以约30％的比例存在于气体中， -92％。