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1.发明授权Embedded DRAM memory cell with additional patterning layer for improved strap formation 有权具有附加图形层的嵌入式DRAM存储单元，用于改善表带形成公开(公告)号：US08426268B2
公开(公告)日：2013-04-23
申请号：US12698293
申请日：2010-02-02
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.
摘要翻译： 本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。 该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。 沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。 然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。 然后蚀刻层状半导体结构。 图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。 通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。
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2.发明授权公开(公告)号：US08003488B2
公开(公告)日：2011-08-23
申请号：US11861614
申请日：2007-09-26
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/1203
摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.
摘要翻译： 在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。 在深沟槽中形成导电沟槽填充区域。 施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。 具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。 对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。 去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。 另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。
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3.发明申请公开(公告)号：US20090079027A1
公开(公告)日：2009-03-26
申请号：US11861614
申请日：2007-09-26
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/1087 , H01L21/84 , H01L27/1203
摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.
摘要翻译： 在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。 在深沟槽中形成导电沟槽填充区域。 施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。 具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。 对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。 去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。 另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。
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4.发明申请EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION 有权嵌入式DRAM记忆体与附加图案层，用于改进的形成公开(公告)号：US20100193852A1
公开(公告)日：2010-08-05
申请号：US12698293
申请日：2010-02-02
IPC分类号： H01L27/108 , H01L21/8242 , G06F17/50
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10867 , H01L27/1087 , H01L29/66181
摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.
摘要翻译： 本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。 该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。 沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。 然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。 然后蚀刻层状半导体结构。 图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。 通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。
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公开(公告)号：US07592245B2
公开(公告)日：2009-09-22
申请号：US12014127
申请日：2008-01-15
IPC分类号： H01L21/44
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译： 本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。 该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。 绝缘子表面水平高于最终结构。 接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。 具体地，多晶硅的厚度大于基板接触孔的尺寸。 接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。 此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。 所述多晶硅的蚀刻不与衬底接触。 绝缘体的过剩被抛光到所需的水平。
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公开(公告)号：US07358172B2
公开(公告)日：2008-04-15
申请号：US11307762
申请日：2006-02-21
IPC分类号： H01L21/44
CPC分类号： H01L21/84
摘要： Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.
摘要翻译： 本文的实施方案提供了一种用于在SOI结构上形成多孔填充衬底接触的方法。 该方法在衬底上形成绝缘体，并在绝缘体内形成衬底接触孔。 绝缘子表面水平高于最终结构。 接下来，执行聚过填料，包括用多晶硅填充衬底接触孔并用多晶硅覆盖绝缘体。 具体地，多晶硅的厚度大于基板接触孔的尺寸。 接下来，蚀刻多晶硅，其中去除多晶硅的一部分，并且其中衬底接触孔部分地被多晶硅填充。 此外，多晶硅的蚀刻在多晶硅的顶部内形成凹形凹部。 所述多晶硅的蚀刻不与衬底接触。 绝缘体的过剩被抛光到所需的水平。
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7.发明申请METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES 失效用于非选择性低温分离隔离反应离子蚀刻的方法，适用于兼容高性能高度集成逻辑器件的混合器件公开(公告)号：US20090189242A1
公开(公告)日：2009-07-30
申请号：US12020887
申请日：2008-01-28
申请人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
发明人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/045 , H01L21/76224
摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
摘要翻译： 公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向 和具有第二结晶取向的体区。 使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个 材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。 可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。
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8.发明申请公开(公告)号：US20090104776A1
公开(公告)日：2009-04-23
申请号：US11874392
申请日：2007-10-18
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/0337 , H01L21/0338 , H01L21/32137 , H01L21/32139
摘要： A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.
摘要翻译： 一种用于形成用于半导体器件的线的方法，包括：在硅衬底上沉积浅沟槽隔离（STI）膜堆叠，在所述STI膜堆叠上沉积多晶硅层，在所述多晶硅层上沉积一层抗反射涂层， 在抗反射涂层上光致抗蚀剂，其中光致抗蚀剂限定线，使用具有低偏压功率的RIE蚀刻抗反射涂层和多晶硅层，去除光致抗蚀剂，去除抗反射涂层，蚀刻STI膜叠层以形成 所述线，其中所述多晶硅层进一步限定所述线。
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9.发明授权Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices 失效用于非选择性浅沟槽隔离反应离子蚀刻的方法，用于图案化与高性能高度集成逻辑器件兼容的混合取向器件公开(公告)号：US07871893B2
公开(公告)日：2011-01-18
申请号：US12020887
申请日：2008-01-28
申请人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
发明人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
IPC分类号： H01L21/76 , H01L21/763
CPC分类号： H01L29/045 , H01L21/76224
摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
摘要翻译： 公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向 和具有第二结晶取向的体区。 使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个 材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。 可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。
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公开(公告)号：US20090047791A1
公开(公告)日：2009-02-19
申请号：US11839681
申请日：2007-08-16
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Munir D. Naeem , William C. Wille , Richard S. Wise
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Munir D. Naeem , William C. Wille , Richard S. Wise
IPC分类号： H01L21/302
CPC分类号： H01L21/3081 , H01L27/10844 , H01L27/11
摘要： A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.
摘要翻译： 公开了蚀刻半导体结构的方法。 该方法可以包括蚀刻半导体器件的SRAM部分，该方法包括：提供硅衬底层，其上的氮化物层，氮化物层上的光学色散层和其上的硅抗反射涂层; 使用图像层蚀刻硅抗反射涂层; 去除图像层; 在去除硅抗反射涂层的同时蚀刻光学色散层; 同时蚀刻光学色散层和氮化物层; 并同时蚀刻光学色散层，氮化物层和硅衬底。
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