公开(公告)号：US07560360B2

公开(公告)日：2009-07-14

申请号：US11468472

申请日：2006-08-30

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

IPC分类号： H01L21/20

CPC分类号： H01L29/945 ,  H01L28/84 ,  H01L29/66181

摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

摘要翻译： 公开了用于增强沟槽电容的方法和如此形成的沟槽电容器。 在一个实施例中，一种方法包括形成沟槽的第一部分; 在第一部分中沉积介电层; 执行包括第一阶段的反应离子蚀刻以蚀刻所述电介质层并在所述沟槽的第一部分的底表面上形成微掩模，以及形成具有粗糙侧壁的所述沟槽的第二部分; 沉积节点电介质; 并用导体填充沟槽。 粗糙的侧壁增加沟槽电容，而不增加处理复杂性或成本。

公开(公告)号：US20080248625A1

公开(公告)日：2008-10-09

申请号：US12120535

申请日：2008-05-14

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

IPC分类号： H01L21/441

CPC分类号： H01L29/945 ,  H01L28/84 ,  H01L29/66181

摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

公开(公告)号：US20080122030A1

公开(公告)日：2008-05-29

申请号：US11468472

申请日：2006-08-30

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Xi Li

IPC分类号： H01L29/86 ,  H01L21/441

CPC分类号： H01L29/945 ,  H01L28/84 ,  H01L29/66181

摘要： Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

摘要翻译： 公开了用于增强沟槽电容的方法和如此形成的沟槽电容器。 在一个实施例中，一种方法包括形成沟槽的第一部分; 在所述第一部分中沉积介电层; 执行包括第一阶段的反应离子蚀刻以蚀刻所述电介质层并在所述沟槽的第一部分的底表面上形成微掩模，以及形成具有粗糙侧壁的所述沟槽的第二部分; 沉积节点电介质; 并用导体填充沟槽。 粗糙的侧壁增加沟槽电容，而不增加处理复杂性或成本。

公开(公告)号：US08426268B2

公开(公告)日：2013-04-23

申请号：US12698293

申请日：2010-02-02

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Byeong Y. Kim ,  Munir D. Naeem

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Byeong Y. Kim ,  Munir D. Naeem

IPC分类号： H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/66181

摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。 该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。 沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。 然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。 然后蚀刻层状半导体结构。 图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。 通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。

公开(公告)号：US08003488B2

公开(公告)日：2011-08-23

申请号：US11861614

申请日：2007-09-26

申请人： Kangguo Cheng ,  Munir D. Naeem ,  David M. Dobuzinsky ,  Byeong Y. Kim

发明人： Kangguo Cheng ,  Munir D. Naeem ,  David M. Dobuzinsky ,  Byeong Y. Kim

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L27/1087 ,  H01L21/84 ,  H01L27/1203

摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.

摘要翻译： 在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。 在深沟槽中形成导电沟槽填充区域。 施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。 具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。 对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。 去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。 另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。

公开(公告)号：US20090079027A1

公开(公告)日：2009-03-26

申请号：US11861614

申请日：2007-09-26

申请人： Kangguo Cheng ,  Munir D. Naeem ,  David M. Dobuzinsky ,  Byeong Y. Kim

发明人： Kangguo Cheng ,  Munir D. Naeem ,  David M. Dobuzinsky ,  Byeong Y. Kim

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L27/1087 ,  H01L21/84 ,  H01L27/1203

摘要： A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently.

摘要翻译： 在绝缘体上半导体（SOI）衬底和其上的衬垫层上形成深沟槽。 在深沟槽中形成导电沟槽填充区域。 施加具有相对于焊盘层的蚀刻选择性的平坦化材料层。 具有与深沟槽的侧壁垂直一致的边缘的焊盘层的一部分被光刻装置暴露。 对平坦化材料层选择性地去除衬垫层的暴露部分，然后通过各向异性蚀刻去除对导电沟槽填充区域选择性的半导体层的暴露部分。 去除平坦化材料层，并且形成具有与原始深沟槽的边缘自对准的下侧壁的浅沟槽隔离结构。 另一个浅沟槽隔离结构可以同时形成在深沟槽的外部。

公开(公告)号：US20100193852A1

公开(公告)日：2010-08-05

申请号：US12698293

申请日：2010-02-02

申请人： Kangguo Cheng ,  David M. Dobuzinsky ,  Byeong Y. Kim ,  Munir D. Naeem

发明人： Kangguo Cheng ,  David M. Dobuzinsky ,  Byeong Y. Kim ,  Munir D. Naeem

IPC分类号： H01L27/108 ,  H01L21/8242 ,  G06F17/50

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L29/66181

摘要： The present invention relates to semiconductor devices, and more particularly to a structure and method for forming memory cells in a semiconductor device using a patterning layer and etch sequence. The method includes forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. By adding the patterning layer over the semiconductor structure during trench type memory cell fabrication, strap resistance and its variation can be reduced, resulting in better DRAM cell operation with less process dependence and improved strap overlay formation.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及使用图形层和蚀刻顺序在半导体器件中形成存储单元的结构和方法。 该方法包括在层状半导体结构中形成沟槽，每个沟槽具有邻近层间半导体结构在沟槽之间的一部分的内侧壁和与内侧壁相对的外侧壁。 沟槽填充有多晶硅，并且图案化层形成在层状半导体结构之上。 然后通过图案化图案将开口图案化，开口暴露沟槽之间的分层半导体结构的部分，并且仅沿着每个沟槽的内侧壁的多晶硅的垂直部分。 然后蚀刻层状半导体结构。 图案化层防止沿着每个沟槽的外侧壁的多晶硅的第二垂直部分被去除。 通过在沟槽型存储单元制造期间在半导体结构上添加图案化层，可以减小带电阻及其变化，从而获得更好的DRAM单元操作，并且具有更少的工艺依赖性和改进的带叠层形成。

公开(公告)号：US08008160B2

公开(公告)日：2011-08-30

申请号：US12017154

申请日：2008-01-21

申请人： Kangguo Cheng ,  Xi Li ,  Richard Wise

发明人： Kangguo Cheng ,  Xi Li ,  Richard Wise

IPC分类号： H01L21/20

CPC分类号： H01L21/26586 ,  H01L27/10867 ,  H01L29/7833

摘要： A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node dielectric covers said first side portion and said second side portion; depositing a first conductive layer over said node dielectric; performing an ion implantation or ion bombardment at an angle into a portion of said node dielectric, thereby removing said portion of said node dielectric from said first side portion of said deep trench; and depositing a second conductive layer over said first conductive layer, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. A trench device structure having a single-side buried strap is also provided. The device structure includes a semiconductor substrate having a deep trench therein; and a first conductive layer and a second conductive layer sequentially disposed on said deep trench, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate.

摘要翻译： 提供了一种形成具有单面埋入带的沟槽器件结构的方法。 该方法包括在半导体衬底中形成深沟槽，所述深沟槽具有第一侧部分和第二侧部分; 在所述深沟槽上沉积节点电介质，其中所述节点电介质覆盖所述第一侧部分和所述第二侧部分; 在所述节点电介质上沉积第一导电层; 以一定角度进行离子注入或离子轰击到所述节点电介质的一部分中，从而从所述深沟槽的所述第一侧部分移除所述节点电介质的所述部分; 以及在所述第一导电层上沉积第二导电层，其中所述第二导电层超出所述半导体衬底的一部分。 还提供了具有单面埋置带的沟槽器件结构。 该器件结构包括其中具有深沟槽的半导体衬底; 以及顺序地设置在所述深沟槽上的第一导电层和第二导电层，其中所述第二导电层向外延伸到所述半导体衬底的一部分中。

公开(公告)号：US07892928B2

公开(公告)日：2011-02-22

申请号：US11690258

申请日：2007-03-23

申请人： Kangguo Cheng ,  Xi Li ,  Richard Stephen Wise

发明人： Kangguo Cheng ,  Xi Li ,  Richard Stephen Wise

IPC分类号： H01L21/336

CPC分类号： H01L21/67069 ,  H01J37/32733 ,  H01J2237/20207 ,  H01L21/3086 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/78654

摘要： A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer.

摘要翻译： 制造不对称间隔物的方法，使用不对称间隔物制造的结构和用于制造不对称间隔物的装置。 该方法包括：在基底上形成具有顶表面和相对的第一和第二侧壁并具有平行于侧壁的纵向轴线的结构; 在所述基底的顶表面，所述结构的顶表面和所述结构的侧壁上形成共形层; 相对于反应离子通量使基板围绕纵向轴线倾斜，反应离子的流量以锐角撞击共形层; 以及将所述保形层暴露于所述反应性离子的通量，直到所述保形层从所述结构的顶表面去除并且所述衬底的顶表面在所述第一侧壁上离开第一间隔物，并在所述第二侧壁上留下第二间隔物，所述第一 间隔物比第二间隔物薄。

公开(公告)号：US20090017584A1

公开(公告)日：2009-01-15

申请号：US11776710

申请日：2007-07-12

申请人： Kangguo Cheng ,  Xi Li ,  Richard S. Wise

发明人： Kangguo Cheng ,  Xi Li ,  Richard S. Wise

IPC分类号： H01L29/786

CPC分类号： H01L29/66795 ,  H01L29/785

摘要： A process for finFET spacer formation generally includes depositing, in order, a conformnal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure.

摘要翻译： 用于finFET间隔物形成的方法通常包括依次将共形衬垫材料，共形隔离材料和保形封盖材料沉积到finFET结构上; 倾斜地将掺杂剂离子注入围绕栅极结构的覆盖层的部分; 围绕源极和漏极区域选择性地去除未掺杂的封盖材料; 选择性地去除间隔物材料的暴露部分; 选择性地去除封盖材料的暴露部分; 各向异性地去除间隔物材料的一部分，以露出栅极材料的顶表面并将间隔物材料隔离到栅极结构的侧壁; 以及从翅片上去除氧化物衬垫以在finFET结构上形成间隔物。