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    Video signal processing device for automatically adjusting phase of sampling clocks
    1.
    发明授权
    Video signal processing device for automatically adjusting phase of sampling clocks 失效
    用于自动调整采样时钟相位的视频信号处理装置

    公开(公告)号：US06917388B2

    公开(公告)日：2005-07-12

    申请号：US10071148

    申请日：2002-02-11

    申请人： Kazutaka Naka ,  Atsushi Maruyama ,  Hiroyuki Urata ,  Masaaki Iwanaga

    发明人： Kazutaka Naka ,  Atsushi Maruyama ,  Hiroyuki Urata ,  Masaaki Iwanaga

    IPC分类号： G09G5/18 ,  H03L7/081 ,  H03L7/199 ,  H04N5/04 ,  H04N5/12 ,  H04N5/20 ,  H03L1/12 ,  H03M1/12 ,  H04N7/00 ,  H04N9/475

    CPC分类号： H04N5/04 ,  G09G5/18 ,  H03L7/081 ,  H03L7/199 ,  H04N5/126 ,  H04N5/20

    摘要： In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.

    摘要翻译： 在视频信号处理装置中，代表具有黑白两种灰度的测试图形的输入视频信号VO与A / D转换器4同步地与写入控制电路中产生的采样时钟同步地转换为8位数据 5，然后存储在存储器6中。 MPU9读出存储在存储器6中的视频信号的有效区域中的像素数据，并且计算其值大于预定值的白电平图像元数据的平均值与平均值之间的差ΔT 其值小于预定值的黑电平图像元素数据以及白电平图像元素数据的方差与黑电平图像元素数据的方差之间的总方差VT。 MPU9控制在写入控制电路5中产生的采样时钟的相位，使得AT最大，VT最小。 通过此操作，当视频信号转换为数字数据时，采样相位可以自动调整为最佳值。

    Video signal processing device for automatically adjusting phase of sampling clocks
    2.
    发明授权
    Video signal processing device for automatically adjusting phase of sampling clocks 失效
    用于自动调整采样时钟相位的视频信号处理装置

    公开(公告)号：US06707503B1

    公开(公告)日：2004-03-16

    申请号：US09225348

    申请日：1999-01-05

    申请人： Kazutaka Naka ,  Atsushi Maruyama ,  Hiroyuki Urata ,  Masaaki Iwanaga

    发明人： Kazutaka Naka ,  Atsushi Maruyama ,  Hiroyuki Urata ,  Masaaki Iwanaga

    IPC分类号： H03L700

    CPC分类号： H04N5/04 ,  G09G5/18 ,  H03L7/081 ,  H03L7/199 ,  H04N5/126 ,  H04N5/20

    摘要： In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.

    摘要翻译： 在视频信号处理装置中，代表具有黑白两种灰度的测试图形的输入视频信号VO与A / D转换器4同步地与写入控制电路中产生的采样时钟同步地转换为8位数据 MPU 9存储在存储器6中的视频信号的有效区域中读出图像元素数据，并计算出在其值为0的白电平像素数据的平均值之间的差ΔT 大于预定值，并且其值小于预定值的黑电平图像元素数据的平均值，以及白电平图像元素数据的方差与黑电平的方差之间的总方差VT 图片元素数据。 MPU9控制在写入控制电路5中产生的采样时钟的相位，使得AT最大，VT最小。 通过此操作，当视频信号转换为数字数据时，采样相位可以自动调整为最佳值。

    Video signal processing device for automatically adjusting phase of sampling clocks
    3.
    发明授权
    Video signal processing device for automatically adjusting phase of sampling clocks 失效
    用于自动调整采样时钟相位的视频信号处理装置

    公开(公告)号：US5990968A

    公开(公告)日：1999-11-23

    申请号：US687240

    申请日：1996-07-25

    申请人： Kazutaka Naka ,  Atsushi Maruyama ,  Hiroyuki Urata ,  Masaaki Iwanaga

    发明人： Kazutaka Naka ,  Atsushi Maruyama ,  Hiroyuki Urata ,  Masaaki Iwanaga

    IPC分类号： G06F1/10 ,  G09G5/18 ,  H03L7/081 ,  H03L7/091 ,  H03L7/199 ,  H04N5/04 ,  H04N5/12 ,  H04N5/20 ,  H04N5/66 ,  H04N9/64 ,  H03L7/00 ,  H04L7/00

    CPC分类号： H04N9/64 ,  G09G5/18 ,  H03L7/081 ,  H04N5/04 ,  H04N5/126 ,  H04N5/20 ,  H03L7/091 ,  H03L7/199

    摘要： In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum. With this operation, the sampling phase can be automatically adjusted to the optimum value when the video signal is converted to digital data.

    摘要翻译： 在视频信号处理装置中，代表具有黑白两种灰度的测试图形的输入视频信号VO与A / D转换器4同步地与写入控制电路中产生的采样时钟同步地转换为8位数据 MPU 9存储在存储器6中的视频信号的有效区域中读出图像元素数据，并计算出在其值为0的白电平像素数据的平均值之间的差ΔT 大于预定值，并且其值小于预定值的黑电平图像元素数据的平均值，以及白电平图像元素数据的方差与黑电平的方差之间的总方差VT 图片元素数据。 MPU9控制在写入控制电路5中产生的采样时钟的相位，使得AT最大，VT最小。 通过此操作，当视频信号转换为数字数据时，采样相位可以自动调整为最佳值。

    Image processing apparatus with change over of clock signals
    4.
    发明授权
    Image processing apparatus with change over of clock signals 失效
    具有时钟信号切换的图像处理装置

    公开(公告)号：US5541665A

    公开(公告)日：1996-07-30

    申请号：US362241

    申请日：1994-12-22

    申请人： Hiroyuki Urata ,  Masahiro Eto ,  Atsushi Maruyama ,  Fumio Inoue ,  Masanori Ogino ,  Kiyoshi Yamamoto ,  Kazutaka Naka ,  Masaaki Iwanaga

    发明人： Hiroyuki Urata ,  Masahiro Eto ,  Atsushi Maruyama ,  Fumio Inoue ,  Masanori Ogino ,  Kiyoshi Yamamoto ,  Kazutaka Naka ,  Masaaki Iwanaga

    IPC分类号： H04N5/12 ,  H04N5/46 ,  H04N7/01 ,  H04N7/12 ,  H04N11/24 ,  H04N5/00 ,  H04N7/015 ,  H04N7/46

    CPC分类号： H04N7/125 ,  H04N11/006 ,  H04N7/0105 ,  H04N5/126 ,  H04N5/46

    摘要： In order to enable sampling of high definition still video signals in addition to common video signals, a function is added for sampling video signals with every other plurality of picture elements as an interval to an image processing apparatus without using a sampling circuit which requires high speed operations. The invention is also intended to change over between two circuits that is, a circuit for using a picture element clock regenerated by a PLL circuit as a sampling clock for analog to digital converters and a circuit for using a clock obtained by dividing the picture element clock as a sampling clock for the analog to digital converters to sample video signals with every other plurality of picture elements as an interval. Thus, it is possible to carry out sampling of high definition video signals with high frequencies in addition to common video signals without necessity of raising the operating speed of the sampling circuit.

    摘要翻译： 为了能够对公共视频信号进行高分辨率静止图像信号的采样，添加了将图像信号与其他多个像素一起作为图像处理装置的间隔进行采样的功能，而不使用需要高速的采样电路 操作。 本发明还旨在在两个电路之间切换，即，用于使用由PLL电路再生的像素时钟作为模数转换器的采样时钟的电路和用于使用通过将图像元素时钟 作为模数转换器的采样时钟，以与其他多个像素作为间隔采样视频信号。 因此，除了公共视频信号之外，可以对高频高清晰度视频信号进行采样，而不需要提高采样电路的工作速度。

    Processor for converting pixel number of video signal and display apparatus using the same
    6.
    发明授权
    Processor for converting pixel number of video signal and display apparatus using the same 失效
    用于转换视频信号的像素数和使用其的显示装置的处理器

    公开(公告)号：US5986635A

    公开(公告)日：1999-11-16

    申请号：US837747

    申请日：1997-04-22

    申请人： Kazutaka Naka ,  Atsushi Maruyama ,  Hiroyuki Urata ,  Haruki Takata

    发明人： Kazutaka Naka ,  Atsushi Maruyama ,  Hiroyuki Urata ,  Haruki Takata

    IPC分类号： G09G3/20 ,  G09G5/00

    CPC分类号： G09G5/008 ,  G09G5/005 ,  G09G2300/026 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0442 ,  G09G5/006

    摘要： A video signal processor which includes a circuit for converting the number of lines in a digitized video signal, a circuit for generating a display dot clock, a circuit for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation;frck/N=fck/M=fhowhere M and N are natural numbers satisfying M.noteq.N.

    摘要翻译： 一种视频信号处理器，包括用于转换数字化视频信号中的行数的电路，用于产生显示点时钟的电路，用于输出经过行数转换的模拟像素数据的电路，并且具有不同于 显示点时钟和用于平滑模拟像素数据的电路; 并且其中显示点时钟的频率fck，模拟像素数据的输出频率frk和水平同步信号的频率fho满足等式; frck / N = fck / M = fho其中M和N是满足的自然数 M NOTEQUAL N.

    Scalable CRT display device and phase synchronous circuit for use in display device
    7.
    发明授权
    Scalable CRT display device and phase synchronous circuit for use in display device 失效
    可扩展的CRT显示设备和用于显示设备的相位同步电路

    公开(公告)号：US5712532A

    公开(公告)日：1998-01-27

    申请号：US306711

    申请日：1994-09-15

    申请人： Masanori Ogino ,  Yoshiyuki Imoto ,  Kunio Umehara ,  Jiro Kawasaki ,  Kiyoshi Yamamoto ,  Miyuki Ikeda ,  Kazutaka Naka

    发明人： Masanori Ogino ,  Yoshiyuki Imoto ,  Kunio Umehara ,  Jiro Kawasaki ,  Kiyoshi Yamamoto ,  Miyuki Ikeda ,  Kazutaka Naka

    IPC分类号： G09G1/04 ,  H04N3/233 ,  H04N3/26 ,  H04N3/27 ,  H04N9/64 ,  H01V29/98

    CPC分类号： G09G1/04 ,  H04N3/2335 ,  H04N3/26 ,  H04N3/27 ,  H04N9/645

    摘要： A CRT display device capable of displaying a signal from the existing image signal source, in which a vertical frequency is approximately fixed and a horizontal frequency is widely distributed beyond a ratio of 3:1, on one image screen. The CRT display device includes a scan converter unit and a display unit. The scan converter unit includes an output horizontal frequency unifying circuit, a horizontal blanking period ratio converting circuit, a vertical frequency converting unit and a vertical blanking period ratio converting circuit. The display unit includes a vertical deflection circuit and a circuit for correcting a vertical S-shaped distortion. In a phase synchronous circuit, a lock-out detector is connected to an output of a three state output digital phase detector, and on the basis of an output thereof, a switch is subjected to the "ON"/"OFF" control. For a period of time when an output of the lock-out detector indicates a lock-out state, a loop gain of the PLL is increased and the pull-in time is shortened. For the remaining periods of time, i.e., in the steady state, the loop gain is decreased and the noise resistance characteristics are improved.

    摘要翻译： 一种CRT显示装置，其能够显示来自现有图像信号源的信号，其中垂直频率近似固定，并且水平频率被广泛地分布在超过比例3：1的一个图像屏幕上。 CRT显示装置包括扫描转换器单元和显示单元。 扫描转换器单元包括输出水平频率统一电路，水平消隐周期比变换电路，垂直频率转换单元和垂直消隐周期比变换电路。 显示单元包括垂直偏转电路和用于校正垂直S形失真的电路。 在相位同步电路中，锁定检测器连接到三态输出数字相位检测器的输出，并且基于其输出，开关进行“接通”/“断开”控制。 在锁定检测器的输出指示锁定状态的一段时间内，PLL的环路增益增加，并且引入时间缩短。 对于剩余时间段，即处于稳定状态，环路增益减小，并且提高了抗噪声特性。