公开(公告)号：US08495532B2

公开(公告)日：2013-07-23

申请号：US13076649

申请日：2011-03-31

申请人： Ke-Ying Su ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

发明人： Ke-Ying Su ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/12 ,  Y02P90/265

摘要： A method includes approximating a physical characteristic of a semiconductor substrate with a frequency-dependent circuit, and creating a technology file for the semiconductor substrate based on the frequency-dependent circuit. The physical characteristic of the semiconductor substrate identified by one of an electromagnetic simulation or a silicon measurement. The technology file is adapted for use by an electronic design automation tool to create a netlist for the semiconductor substrate and is stored in a non-transient computer readable storage medium.

摘要翻译： 一种方法包括使用频率相关电路近似半导体衬底的物理特性，并且基于频率相关电路创建用于半导体衬底的技术文件。 通过电磁仿真或硅测量之一识别的半导体衬底的物理特性。 技术文件适用于电子设计自动化工具，用于创建半导体衬底的网表，并存储在非瞬态计算机可读存储介质中。

公开(公告)号：US08453095B2

公开(公告)日：2013-05-28

申请号：US13176823

申请日：2011-07-06

申请人： Ke-Ying Su ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

发明人： Ke-Ying Su ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5077 ,  G06F17/5081

摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.

摘要翻译： 一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感 基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线 模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

公开(公告)号：US20130014070A1

公开(公告)日：2013-01-10

申请号：US13176823

申请日：2011-07-06

申请人： Ke-Ying SU ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

发明人： Ke-Ying SU ,  Ching-Shun Yang ,  Jui-Feng Kuan ,  Hsiao-Shu Chao ,  Yi-Kan Cheng ,  Huang-Yu Chen ,  Chung-Hsing Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5077 ,  G06F17/5081

摘要： A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings.

摘要翻译： 一种方法包括创建包括用于集成电路的数据的技术文件，所述集成电路包括耦合到插入器的至少一个管芯以及所述至少一个管芯和所述插入器之间的布线，b）创建包括接近电容或电感 基于所述技术文件，在所述至少一个管芯中和所述插入器中的导体之间的耦合，c）基于所述网表来模拟所述集成电路的性能，d）基于所述网表调整所述至少一个管芯和所述插入器之间的布线 模拟以减少电容或电感耦合中的至少一个，以及e）重复步骤c）和d）以优化电容或电感耦合中的至少一个。

公开(公告)号：US20130139121A1

公开(公告)日：2013-05-30

申请号：US13366756

申请日：2012-02-06

申请人： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

发明人： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

摘要翻译： 本公开涉及用于产生用于RC提取的穿硅通孔（TSV）模型的方法和装置，其精确地对包括一个或多个TSV的插入器衬底进行建模。 在一些实施例中，通过产生具有对TSV进行建模的子电路的插入器晶片模型来执行方法。 子电路可以补偿由EDA工具执行的传统TSV模型的电阻和电容提取的限制。 在一些实施例中，子电路耦合到模型的浮动公共节点。 浮动公共节点使得插入器晶片模型能够考虑插入器内的电容耦合。 改进的插入器晶片模型使得能够利用一个或多个TSV对插入件进行精确的RC提取，由此提供在GDS和APR流之间一致的插入器晶片模型。

公开(公告)号：US08621409B2

公开(公告)日：2013-12-31

申请号：US13459288

申请日：2012-04-30

申请人： Hui Yu Lee ,  Feng Wei Kuo ,  Ching-Shun Yang ,  Yi-Kan Cheng ,  Jui-Feng Kuan

发明人： Hui Yu Lee ,  Feng Wei Kuo ,  Ching-Shun Yang ,  Yi-Kan Cheng ,  Jui-Feng Kuan

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5081

摘要： A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

摘要翻译： 一种方法包括从半导体电路的第一布局提取第一网表并基于第一网表估计与布局有关的效果数据。 基于使用电子设计自动化工具的第一网表执行半导体电路的第一仿真，并且基于使用电子设计自动化工具的电路示意图来执行半导体电路的第二仿真。 计算至少一个与布局相关的效果的重量和灵敏度，并且基于重量和灵敏度来调整半导体电路的第一布局以提供半导体电路的第二布局。 第二布局存储在非瞬态存储介质中。

公开(公告)号：US08607179B2

公开(公告)日：2013-12-10

申请号：US13366756

申请日：2012-02-06

申请人： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

发明人： Ze-Ming Wu ,  Ching-Shun Yang ,  Ke-Ying Su ,  Hsiao-Shu Chao

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows.

公开(公告)号：US08707245B2

公开(公告)日：2014-04-22

申请号：US13406108

申请日：2012-02-27

申请人： Ching-Shun Yang ,  Ze-Ming Wu ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

发明人： Ching-Shun Yang ,  Ze-Ming Wu ,  Hsiao-Shu Chao ,  Yi-Kan Cheng

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： G06F17/5081 ,  G03F7/00 ,  G06F17/5036 ,  G06F2217/82

摘要： In a semiconductor device design method performed by at least one processor, first and second electrical components are extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second electrical components in the semiconductor substrate. Parasitic parameters of a coupling in the semiconductor substrate between the first and second electrical components are extracted using a first tool. Intrinsic parameters of the first and second electrical components are extracted using a second tool different from the first tool. The extracted parasitic parameters and intrinsic parameters are combined into a model of the semiconductor device. The parasitic parameters of the coupling are extracted based on a model of the coupling included in the second tool.

摘要翻译： 在由至少一个处理器执行的半导体器件设计方法中，从半导体器件的布局中提取第一和第二电子部件。 半导体器件具有半导体衬底和半导体衬底中的第一和第二电子部件。 使用第一工具提取第一和第二电气部件之间的半导体衬底中的耦合的寄生参数。 使用与第一工具不同的第二工具提取第一和第二电气部件的固有参数。 提取的寄生参数和固有参数被组合成半导体器件的模型。 基于包括在第二工具中的耦合模型，提取耦合的寄生参数。

公开(公告)号：US08694938B2

公开(公告)日：2014-04-08

申请号：US13534526

申请日：2012-06-27

申请人： Ching-Shun Yang ,  Chih Ming Yang ,  Wei-Yi Hu ,  Yi-Kan Cheng

发明人： Ching-Shun Yang ,  Chih Ming Yang ,  Wei-Yi Hu ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.

摘要翻译： 除其他之外，提供一个或多个技术和/或系统用于将分立设备建模为宏设备。 也就是说，分立器件可以包括一个或多个寄生元件，例如寄生电阻和/或电容。 由于寄生元件的值在分立器件的预仿真期间是未知的，所以可将分立器件建模为宏器件，可在预仿真期间使用以考虑寄生元件。 例如，可以使用诸如通道长度的指定参数来获得指定离散器件的一个或多个寄生元件的预测值的一组RC值。 可以使用一组RC值将离散器件建模为宏器件。 以这种方式，可以在预仿真期间使用宏器件来考虑分立器件的寄生元件的寄生效应。

公开(公告)号：US20140007028A1

公开(公告)日：2014-01-02

申请号：US13534526

申请日：2012-06-27

申请人： Ching-Shun Yang ,  Chih Ming Yang ,  Wei-Yi Hu ,  Yi-Kan Cheng

发明人： Ching-Shun Yang ,  Chih Ming Yang ,  Wei-Yi Hu ,  Yi-Kan Cheng

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Among other things, one or more techniques and/or systems are provided for modeling a discrete device as a macro device. That is, the discrete device can comprise one or more parasitic elements, such as parasitic resistances and/or capacitances. Because values of the parasitic elements are unknown during pre-simulation of the discrete device, the discrete device can be modeled as a macro device, which can be used during pre-simulation to take into account the parasitic elements. For example, specified parameters, such as channel length, can be used to obtain a set of RC values that specify predicted values for the one or more parasitic elements of the discrete device. The discrete device can be modeled as the macro device using the set of RC values. In this way, the macro device can be used during pre-simulation to take into account the parasitic effects of parasitic elements of the discrete device.

摘要翻译： 除其他之外，提供一个或多个技术和/或系统用于将分立设备建模为宏设备。 也就是说，分立器件可以包括一个或多个寄生元件，例如寄生电阻和/或电容。 由于寄生元件的值在分立器件的预仿真期间是未知的，所以可将分立器件建模为宏器件，可在预仿真期间使用以考虑寄生元件。 例如，可以使用诸如通道长度的指定参数来获得指定离散器件的一个或多个寄生元件的预测值的一组RC值。 可以使用一组RC值将离散器件建模为宏器件。 以这种方式，可以在预仿真期间使用宏器件来考虑分立器件的寄生元件的寄生效应。

公开(公告)号：US07283101B2

公开(公告)日：2007-10-16

申请号：US10703331

申请日：2003-11-07

申请人： Peter John Bisiules ,  Ching-Shun Yang

发明人： Peter John Bisiules ,  Ching-Shun Yang

IPC分类号： H01Q21/00

CPC分类号： H01Q1/246 ,  H01Q9/0414 ,  H01Q9/0457 ,  H01Q9/0464 ,  H01Q21/28

摘要： A multiband base station antenna for communicating with a plurality of terrestrial mobile devices is described. The antenna including one or modules, each module including a low frequency ring element; and a high frequency dipole element superposed with the low frequency ring element. The element includes a ground plane; and a feed probe directed away from the ground plane and having a coupling part positioned proximate to the ring to enable the feed probe to electromagnetically couple with the ring. A dielectric clip provides a spacer between the feed probe and the ring, and also connects the ring to the ground plane. An antenna element is also described including a ring, and one or more feed probes extending from the ring, wherein the ring and feed probe(s) are formed from a unitary piece.

摘要翻译： 描述了用于与多个地面移动设备进行通信的多频带基站天线。 所述天线包括一个或多个模块，每个模块包括低频环形元件; 以及与低频环形元件重叠的高频偶极子元件。 元件包括接地平面; 以及馈送探针，其远离接地平面并且具有靠近环定位的耦合部分，以使馈电探针与环电磁耦合。 电介质夹在馈电探针和环之间提供间隔物，并将环连接到接地平面。 还描述了一种天线元件，其包括环和从环延伸的一个或多个馈送探针，其中环和馈送探针由整体构成。