利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.029 秒)

    Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM)
    1.
    发明授权
    Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM) 有权
    在基于DRAM的内容可寻址存储器（CAM）中组合刷新操作与奇偶校验的方法

    公开(公告)号：US06760881B2

    公开(公告)日：2004-07-06

    申请号：US09981081

    申请日：2001-10-16

    申请人： Kevin A. Batson ,  Robert E. Busch ,  Albert M. Chu ,  Ezra D. B. Hall

    发明人： Kevin A. Batson ,  Robert E. Busch ,  Albert M. Chu ,  Ezra D. B. Hall

    IPC分类号： G11C2900

    CPC分类号： G11C7/24 ,  G11C11/406 ,  G11C15/043

    摘要： A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.

    摘要翻译： 公开了一种用于将刷新操作与用于基于DRAM的内容可寻址存储器（CAM）的奇偶验证相结合的方法。 在本发明的示例性实施例中，该方法包括实现存储器刷新操作并检查CAM内包含的单词。 确定该单词中包含的数据是否构成有效数据。 如果单词中包含的数据不构成有效数据，则旁路奇偶校验。 然而，如果单词中包含的数据确实构成有效数据，则实现奇偶校验验证。 奇偶校验验证还包括读取单词中包含的数据，从包含在单词内的数据生成奇偶校验位，并将生成的奇偶校验位与先前存储的奇偶校验位进行比较。 如果执行奇偶校验验证，并且如果生成的奇偶校验位与先前存储的奇偶校验位不匹配，则该单词中包含的数据无效。

    CAM cell with interdigitated search and bit lines
    2.
    发明授权
    CAM cell with interdigitated search and bit lines 失效
    CAM单元具有交叉搜索和位线

    公开(公告)号：US06760240B2

    公开(公告)日：2004-07-06

    申请号：US10065822

    申请日：2002-11-22

    申请人： Robert E. Busch ,  Albert M. Chu ,  Ezra D. B. Hall ,  Paul C. Parries ,  Daryl M. Seizter

    发明人： Robert E. Busch ,  Albert M. Chu ,  Ezra D. B. Hall ,  Paul C. Parries ,  Daryl M. Seizter

    IPC分类号： G11C1500

    CPC分类号： G11C15/04

    摘要： A method and structure for an array of content addressable memory (CAM) cells is disclosed. Each of the CAM cells has a search line and a bitline parallel to the search line. Across the array, search lines and bit lines of the CAM cells are interdigitated so that the search lines and bitlines alternate across the array. CAM cell macro's are inverted with respect to adjacent macros to balance parasitic capacitances across the array.

    摘要翻译： 公开了一种用于内容可寻址存储器（CAM）单元阵列的方法和结构。 每个CAM单元具有搜索线和平行于搜索线的位线。 跨阵列，CAM单元的搜索行和位线是交叉的，以便搜索行和位线在数组之间交替。 CAM单元宏相对于相邻的宏反转，以平衡阵列上的寄生电容。

    System and method for wireless and dynamic intra-process measurement of integrated circuit parameters
    3.
    发明授权
    System and method for wireless and dynamic intra-process measurement of integrated circuit parameters 有权
    集成电路参数的无线和动态过程内测量的系统和方法

    公开(公告)号：US08239811B2

    公开(公告)日：2012-08-07

    申请号：US12053705

    申请日：2008-03-24

    申请人： Theodoros E. Anemikos ,  Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Anthony J. Perri ,  Sebastian T. Ventrone

    发明人： Theodoros E. Anemikos ,  Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Anthony J. Perri ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50 ,  G06F11/22

    CPC分类号： H04Q9/00 ,  H01L22/12 ,  H01L22/14 ,  H01L22/26 ,  H01L23/64 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.

    摘要翻译： 公开了允许集成电路参数的无线和动态内部处理（即，在处理步骤期间和/或之间）的系统和方法的实施例。 实施例结合了对一个或多个物理或电气集成电路参数中的过程变化具有预定灵敏度的无源电路（例如电感器 - 电容 - 电阻（LCR）电路谐振器）的使用。 无源电路可以在和/或处理步骤之间进行无线询问。 然后，将无源电路响应于询问所表现的实际行为与没有过程变化的最佳电路的预期行为进行比较，以便确定一个或多个参数。 还公开了可用于实现所公开的系统和方法实施例的示例性无源电路的实施例。

    Integrated circuit chip design flow methodology including insertion of on-chip or scribe line wireless process monitoring and feedback circuitry
    5.
    发明授权
    Integrated circuit chip design flow methodology including insertion of on-chip or scribe line wireless process monitoring and feedback circuitry 有权
    集成电路芯片设计流程方法，包括插入片上或划线无线过程监控和反馈电路

    公开(公告)号：US08097474B2

    公开(公告)日：2012-01-17

    申请号：US12343686

    申请日：2008-12-24

    申请人： Theodoros Anemikos ,  Ezra D. B. Hall ,  Sebastian T. Ventrone

    发明人： Theodoros Anemikos ,  Ezra D. B. Hall ,  Sebastian T. Ventrone

    IPC分类号： H01L21/66

    CPC分类号： G06F17/5045 ,  G01R31/2884 ,  G01R31/3025 ,  G06F2217/12 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

    摘要： Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).

    摘要翻译： 公开了设计和制造系统以及相关方法的实施例，其允许在晶片制造期间进行设计分析和插入过程内监控电路。 这些实施例使用预定义的内部过程监视电路库和将不同监控电路与不同IC芯片组件链接的互相关表。 具体地，这些实施例分析集成电路芯片设计数据以识别设计到芯片中的部件。 然后，从库中选择一个或多个进程内监控电路，并且修改设计数据以包括所选择的监视电路。

    Passive resonator, a system incorporating the passive resonator for real-time intra-process monitoring and control and an associated method
    6.
    发明授权
    Passive resonator, a system incorporating the passive resonator for real-time intra-process monitoring and control and an associated method 失效
    无源谐振器，一种结合无源谐振器的实时内部监控和控制系统及相关方法

    公开(公告)号：US08700199B2

    公开(公告)日：2014-04-15

    申请号：US13052346

    申请日：2011-03-21

    申请人： Mete Erturk ,  Ezra D. B. Hall ,  Kirk D. Peterson

    发明人： Mete Erturk ,  Ezra D. B. Hall ,  Kirk D. Peterson

    IPC分类号： G06F19/00

    CPC分类号： H01L22/14 ,  H01L22/26 ,  H01L23/5227 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a resonator made up of three sections (i.e., first, second and third sections) of a semiconductor layer. The second section has an end abutting the first section, a middle portion (i.e., an inductor portion) coiled around the first section and another end abutting the third section. The first and third sections exhibit a higher capacitance to the wafer substrate than the second section. Also disclosed are a process control system and method that incorporate one or more of these resonators. Specifically, during processing by a processing tool, wireless interrogation unit(s) detect the frequency response of resonator(s) in response to an applied stimulus. The detected frequency response is measured and used as the basis for making real-time adjustments to input settings on the processing tool (e.g., as the basis for making real-time adjustments to the temperature setting(s) of an anneal chamber).

    摘要翻译： 公开了由半导体层的三个部分（即第一，第二和第三部分）构成的谐振器。 第二部分具有邻接第一部分的端部，围绕第一部分卷绕的中间部分（即电感器部分），以及抵靠第三部分的另一端部。 与第二部分相比，第一和第三部分显示比晶片衬底更高的电容。 还公开了并入这些谐振器中的一个或多个的过程控制系统和方法。 具体地，在处理工具的处理期间，无线询问单元响应于所施加的刺激来检测谐振器的频率响应。 检测到的频率响应被测量并用作对处理工具上的输入设置进行实时调整的基础（例如，作为对退火室的温度设置进行实时调整的基础）。

    Wide dynamic range image sensor utilizing switch current source at pre-determined switch voltage per pixel
    7.
    发明授权
    Wide dynamic range image sensor utilizing switch current source at pre-determined switch voltage per pixel 有权
    宽动态范围图像传感器利用每个像素预定开关电压的开关电流源

    公开(公告)号：US08130298B2

    公开(公告)日：2012-03-06

    申请号：US12027283

    申请日：2008-02-07

    申请人： Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Paul A. Niekrewicz

    发明人： Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Paul A. Niekrewicz

    IPC分类号： H04N3/14 ,  H04N5/335

    CPC分类号： H04N5/235 ,  H04N5/35527 ,  H04N5/3745

    摘要： Disclosed are embodiments of a pixel imaging circuit that incorporates a standard photodiode. However, the imaging circuit is modified with a feedback loop to provide a first photo response over a first portion of the light sensing range (e.g., at higher light intensity range) and a second reduced-sensitivity photo response over a second portion of the light sensing range (i.e., at a lower light intensity range), thereby extending the circuits dynamic range of coverage. Also disclosed are embodiments of an associated imaging method and a design structure that is embodied in a machine readable medium and used in the imaging circuit design process.

    摘要翻译： 公开了包含标准光电二极管的像素成像电路的实施例。 然而，成像电路用反馈回路修改以在光感测范围的第一部分（例如，在较高的光强度范围）提供第一光响应，并且在光的第二部分上提供第二灵敏度敏感的光响应 感测范围（即，在较低的光强度范围），从而延长电路的动态覆盖范围。 还公开了相关的成像方法和体现在机器可读介质中并用于成像电路设计过程中的设计结构的实施例。