公开(公告)号：US08700199B2

公开(公告)日：2014-04-15

申请号：US13052346

申请日：2011-03-21

申请人： Mete Erturk ,  Ezra D. B. Hall ,  Kirk D. Peterson

发明人： Mete Erturk ,  Ezra D. B. Hall ,  Kirk D. Peterson

IPC分类号： G06F19/00

CPC分类号： H01L22/14 ,  H01L22/26 ,  H01L23/5227 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a resonator made up of three sections (i.e., first, second and third sections) of a semiconductor layer. The second section has an end abutting the first section, a middle portion (i.e., an inductor portion) coiled around the first section and another end abutting the third section. The first and third sections exhibit a higher capacitance to the wafer substrate than the second section. Also disclosed are a process control system and method that incorporate one or more of these resonators. Specifically, during processing by a processing tool, wireless interrogation unit(s) detect the frequency response of resonator(s) in response to an applied stimulus. The detected frequency response is measured and used as the basis for making real-time adjustments to input settings on the processing tool (e.g., as the basis for making real-time adjustments to the temperature setting(s) of an anneal chamber).

摘要翻译： 公开了由半导体层的三个部分（即第一，第二和第三部分）构成的谐振器。 第二部分具有邻接第一部分的端部，围绕第一部分卷绕的中间部分（即电感器部分），以及抵靠第三部分的另一端部。 与第二部分相比，第一和第三部分显示比晶片衬底更高的电容。 还公开了并入这些谐振器中的一个或多个的过程控制系统和方法。 具体地，在处理工具的处理期间，无线询问单元响应于所施加的刺激来检测谐振器的频率响应。 检测到的频率响应被测量并用作对处理工具上的输入设置进行实时调整的基础（例如，作为对退火室的温度设置进行实时调整的基础）。

公开(公告)号：US08130298B2

公开(公告)日：2012-03-06

申请号：US12027283

申请日：2008-02-07

申请人： Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Paul A. Niekrewicz

发明人： Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Paul A. Niekrewicz

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H04N5/235 ,  H04N5/35527 ,  H04N5/3745

摘要： Disclosed are embodiments of a pixel imaging circuit that incorporates a standard photodiode. However, the imaging circuit is modified with a feedback loop to provide a first photo response over a first portion of the light sensing range (e.g., at higher light intensity range) and a second reduced-sensitivity photo response over a second portion of the light sensing range (i.e., at a lower light intensity range), thereby extending the circuits dynamic range of coverage. Also disclosed are embodiments of an associated imaging method and a design structure that is embodied in a machine readable medium and used in the imaging circuit design process.

摘要翻译： 公开了包含标准光电二极管的像素成像电路的实施例。 然而，成像电路用反馈回路修改以在光感测范围的第一部分（例如，在较高的光强度范围）提供第一光响应，并且在光的第二部分上提供第二灵敏度敏感的光响应 感测范围（即，在较低的光强度范围），从而延长电路的动态覆盖范围。 还公开了相关的成像方法和体现在机器可读介质中并用于成像电路设计过程中的设计结构的实施例。

公开(公告)号：US08239811B2

公开(公告)日：2012-08-07

申请号：US12053705

申请日：2008-03-24

申请人： Theodoros E. Anemikos ,  Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Anthony J. Perri ,  Sebastian T. Ventrone

发明人： Theodoros E. Anemikos ,  Phillip L. Corson ,  Mete Erturk ,  Ezra D. B. Hall ,  Anthony J. Perri ,  Sebastian T. Ventrone

IPC分类号： G06F17/50 ,  G06F11/22

CPC分类号： H04Q9/00 ,  H01L22/12 ,  H01L22/14 ,  H01L22/26 ,  H01L23/64 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.

摘要翻译： 公开了允许集成电路参数的无线和动态内部处理（即，在处理步骤期间和/或之间）的系统和方法的实施例。 实施例结合了对一个或多个物理或电气集成电路参数中的过程变化具有预定灵敏度的无源电路（例如电感器 - 电容 - 电阻（LCR）电路谐振器）的使用。 无源电路可以在和/或处理步骤之间进行无线询问。 然后，将无源电路响应于询问所表现的实际行为与没有过程变化的最佳电路的预期行为进行比较，以便确定一个或多个参数。 还公开了可用于实现所公开的系统和方法实施例的示例性无源电路的实施例。

公开(公告)号：US20120245724A1

公开(公告)日：2012-09-27

申请号：US13052346

申请日：2011-03-21

申请人： Mete Erturk ,  Ezra D.B. Hall ,  Kirk D. Peterson

发明人： Mete Erturk ,  Ezra D.B. Hall ,  Kirk D. Peterson

IPC分类号： H01L29/66 ,  G06F19/00

CPC分类号： H01L22/14 ,  H01L22/26 ,  H01L23/5227 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a resonator made up of three sections (i.e., first, second and third sections) of a semiconductor layer. The second section has an end abutting the first section, a middle portion (i.e., an inductor portion) coiled around the first section and another end abutting the third section. The first and third sections exhibit a higher capacitance to the wafer substrate than the second section. Also disclosed are a process control system and method that incorporate one or more of these resonators. Specifically, during processing by a processing tool, wireless interrogation unit(s) detect the frequency response of resonator(s) in response to an applied stimulus. The detected frequency response is measured and used as the basis for making real-time adjustments to input settings on the processing tool (e.g., as the basis for making real-time adjustments to the temperature setting(s) of an anneal chamber).

摘要翻译： 公开了由半导体层的三个部分（即第一，第二和第三部分）构成的谐振器。 第二部分具有邻接第一部分的端部，围绕第一部分卷绕的中间部分（即电感器部分），以及抵靠第三部分的另一端部。 与第二部分相比，第一和第三部分显示比晶片衬底更高的电容。 还公开了并入这些谐振器中的一个或多个的过程控制系统和方法。 具体地，在处理工具的处理期间，无线询问单元响应于所施加的刺激来检测谐振器的频率响应。 测量检测到的频率响应并将其用作对处理工具上的输入设置进行实时调整的基础（例如，作为对退火室的温度设置进行实时调整的基础）。

公开(公告)号：US08237243B2

公开(公告)日：2012-08-07

申请号：US12552317

申请日：2009-09-02

申请人： Douglas M. Daley ,  Mete Erturk ,  Edward J. Gordon

发明人： Douglas M. Daley ,  Mete Erturk ,  Edward J. Gordon

IPC分类号： H01L29/00

CPC分类号： H01G7/00 ,  G06F17/5054 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： On-chip capacitors with a variable capacitance, as well as design structures for a radio frequency integrated circuit, and method of fabricating and method of tuning on-chip capacitors. The on-chip capacitor includes first and second ports powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. Each of the first and second voltage-controlled units is switched between a first state in which the first and second electrodes are electrically isolated from the first and second ports and a second state. When the first voltage-controlled unit is switched to the second state, the first electrode is electrically connected with the first port. When the second voltage-controlled unit is switched to the second state the second electrode is electrically connected with the second port. The on-chip capacitor has a larger capacitance value when the first and second voltage-controlled units are in the second state.

摘要翻译： 具有可变电容的片上电容器，以及用于射频集成电路的设计结构，以及制造方法和片上电容器的调谐方法。 片上电容器包括由相反极性供电的第一和第二端口，第一和第二电极以及第一和第二电压控制单元。 第一和第二压控单元中的每一个在第一和第二电极与第一和第二端口电隔离的第一状态和第二状态之间切换。 当第一电压控制单元切换到第二状态时，第一电极与第一端口电连接。 当第二电压控制单元切换到第二状态时，第二电极与第二端口电连接。 当第一和第二电压控制单元处于第二状态时，片上电容器具有较大的电容值。

公开(公告)号：US08232173B2

公开(公告)日：2012-07-31

申请号：US12917029

申请日：2010-11-01

申请人： Hanyi Ding ,  Mete Erturk ,  Robert A. Groves ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Anthony K. Stamper

发明人： Hanyi Ding ,  Mete Erturk ,  Robert A. Groves ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Anthony K. Stamper

IPC分类号： H01L21/20

CPC分类号： H01L28/10 ,  H01L21/76898 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

摘要翻译： 具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。 还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括：产生同时形成在衬底中的多个垂直开口的功能性表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口的多个垂直开口中的第二个 高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。

公开(公告)号：US20100022063A1

公开(公告)日：2010-01-28

申请号：US12180789

申请日：2008-07-28

申请人： Mete Erturk ,  Edmund J. Sprogis ,  Anthony K. Stamper

发明人： Mete Erturk ,  Edmund J. Sprogis ,  Anthony K. Stamper

IPC分类号： H01L21/02

CPC分类号： H01F41/041 ,  H01F17/0013 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/16 ,  H01L24/48 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/48463 ,  H01L2224/73257 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2224/05599 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Various methods of forming a passive element such as an inductor raised off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned to be bonded on the first wafer such that the passive elements are raised a distance off the first wafer because of the presence of chip connections such as C4 solder bumps. A gap between the passive elements and the first wafer can be filled with underfill or air. If air is used, a hermetic seal around the gap can be created using chip connections such as C4 solder bumps or other known bonding means to seal the gap.

摘要翻译： 提出了形成无源元件的各种方法，例如从衬底的表面上升起的电感器，以提高无源元件的性能。 可以提供第一晶片，并且从第二晶片切割无源元件。 无源元件翻转，然后对齐以接合在第一晶片上，使得无源元件由于存在诸如C4焊料凸块的芯片连接而离开第一晶片一段距离。 无源元件和第一晶片之间的间隙可以用底部填充物或空气填充。 如果使用空气，则可以使用诸如C4焊料凸块或其它已知的粘合装置之类的芯片连接来密封间隙来创建间隙周围的气密密封。

公开(公告)号：US20090322447A1

公开(公告)日：2009-12-31

申请号：US12146555

申请日：2008-06-26

申请人： Douglas M. Daley ,  Mete Erturk ,  Edward J. Gordon

发明人： Douglas M. Daley ,  Mete Erturk ,  Edward J. Gordon

IPC分类号： H03H7/00 ,  H01L29/00

CPC分类号： H01L27/0688 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03H2001/0092 ,  H01L2924/00

摘要： Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor.

摘要翻译： 包括片上电感器和片上电容器的后端行（BEOL）布线结构以及射频集成电路的设计结构。 制造为不同金属化水平的导电特征的片上电感器和片上电容器彼此垂直对准。 位于片上电感器和衬底之间的片上电容器可以用作片上电感器的法拉第屏蔽。 可选地，BEOL布线结构可以包括位于片上电容器和片上电感器之间或片上电容器与衬底顶表面之间的可选法拉第屏蔽。 BEOL布线结构可以包括能够与片上电容器的电极选择性耦合的至少一个浮动电极，以允许在电路操作期间调谐进一步包括片上电感器的LC谐振器的谐振频率。

公开(公告)号：US20090201394A1

公开(公告)日：2009-08-13

申请号：US12027283

申请日：2008-02-07

申请人： Phillip L. Corson ,  Mete Erturk ,  Ezra D.B. Hall ,  Paul A. Niekrewicz

发明人： Phillip L. Corson ,  Mete Erturk ,  Ezra D.B. Hall ,  Paul A. Niekrewicz

IPC分类号： H04N5/335

CPC分类号： H04N5/235 ,  H04N5/35527 ,  H04N5/3745

摘要： Disclosed are embodiments of a pixel imaging circuit that incorporates a standard photodiode. However, the imaging circuit is modified with a feedback loop to provide a first photo response over a first portion of the light sensing range (e.g., at higher light intensity range) and a second reduced-sensitivity photo response over a second portion of the light sensing range (i.e., at a lower light intensity range), thereby extending the circuits dynamic range of coverage. Also disclosed are embodiments of an associated imaging method and a design structure that is embodied in a machine readable medium and used in the imaging circuit design process.

摘要翻译： 公开了包含标准光电二极管的像素成像电路的实施例。 然而，成像电路用反馈回路修改以在光感测范围的第一部分（例如，在较高的光强度范围）提供第一光响应，并且在光的第二部分上提供第二灵敏度敏感的光响应 感测范围（即，在较低的光强度范围），从而延长电路的动态覆盖范围。 还公开了相关的成像方法和体现在机器可读介质中并用于成像电路设计过程中的设计结构的实施例。

公开(公告)号：US20090184423A1

公开(公告)日：2009-07-23

申请号：US12410728

申请日：2009-03-25

申请人： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

发明人： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

IPC分类号： H01L23/48 ,  H01L21/30

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

摘要翻译： 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。