公开(公告)号：US20250098141A1

公开(公告)日：2025-03-20

申请号：US18595199

申请日：2024-03-04

Applicant: Kioxia Corporation

Inventor： Mutsumi OKAJIMA

IPC: H10B12/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor memory device includes: a substrate; a first wiring; a first semiconductor layer disposed between the substrate and the first wiring; second semiconductor layers disposed between the first semiconductor layer and the first wiring; a first via-wiring connected to the first and the second semiconductor layers; a first memory portion connected to the first semiconductor layer; a first gate electrode opposed to the first semiconductor layer; a second wiring connected to the first gate electrode; connection electrodes connected to the second semiconductor layers; second gate electrodes opposed to the second semiconductor layers; third wirings disposed between the second and the first wiring and connected to the second gate electrodes; a fourth wiring connected to the first memory portion; a fifth wiring connected to the connection electrodes in common; and an insulating layer disposed between the fourth wiring and the fifth wiring.

公开(公告)号：US20230413519A1

公开(公告)日：2023-12-21

申请号：US18179537

申请日：2023-03-07

Applicant: Kioxia Corporation

Inventor： Mutsumi OKAJIMA

IPC: H10B12/00 ,  G11C5/10

CPC classification number: H10B12/312 ,  G11C5/10

Abstract: A semiconductor memory device includes: a memory cell array including memory cells, each including an oxide semiconductor transistor; a first insulating layer disposed above the memory cell array; a first wiring layer disposed between the memory cell array and the first insulating layer; a second insulating layer extending in a vertical direction. The second insulating layer has an annular cross-section. The semiconductor memory device includes a third insulating layer further disposed over the first insulating layer, a portion of the third insulating layer being surrounded by the second insulating layer.

公开(公告)号：US20210225847A1

公开(公告)日：2021-07-22

申请号：US17012676

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Masaharu WADA ,  Mutsumi OKAJIMA ,  Tsuneo INABA ,  Shinji MIYANO

IPC: H01L27/108 ,  G11C11/407

Abstract: A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second, electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.

公开(公告)号：US20240315007A1

公开(公告)日：2024-09-19

申请号：US18592970

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Kotaro NODA ,  Takahiro FUJII ,  Takanori AKITA ,  Mutsumi OKAJIMA

IPC: H10B12/00

CPC classification number: H10B12/33 ,  H10B12/05

Abstract: A semiconductor device includes a first oxide semiconductor layer extending in a first direction, a first wiring extending in a second direction that intersects the first direction and surrounding the first oxide semiconductor layer, a first insulating film provided between the first wiring and the first oxide semiconductor layer, a first conductor provided on the first oxide semiconductor layer, a second wiring provided on the first conductor and extending in a third direction that intersects each of the first direction and the second direction, a first insulating layer in contact with a side surface of the second wiring, and a second insulating layer provided on the first insulating layer and having oxygen permeability lower than oxygen permeability of the first insulating layer.

公开(公告)号：US20240260253A1

公开(公告)日：2024-08-01

申请号：US18423110

申请日：2024-01-25

Applicant: Kioxia Corporation

Inventor： Mutsumi OKAJIMA ,  Takafumi MASUDA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device comprises: a substrate;
memory layers arranged in a first direction intersecting with a surface of the substrate; and a first via wiring extending in the first direction. The memory layers each comprise: a first semiconductor layer electrically connected to the first via wiring; a first gate electrode facing surfaces on one side and the other side in the first direction of the first semiconductor layer; a memory portion which is provided on one side in a second direction intersecting with the first direction with respect to the first semiconductor layer, and is electrically connected to the first semiconductor layer; and a first wiring which is provided on the other side in the second direction with respect to the first semiconductor layer, is electrically connected to the first gate electrode, and extends in a third direction intersecting with the first direction and the second direction.

公开(公告)号：US20230301065A1

公开(公告)日：2023-09-21

申请号：US17901077

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Mutsumi OKAJIMA ,  Keiji IKEDA

IPC: H01L27/108 ,  G11C11/4091

CPC classification number: H01L27/10811 ,  G11C11/4091 ,  H01L27/10873

Abstract: A semiconductor memory device includes: a plate electrode; a plurality of memory capacitors arranged along a front surface of the plate electrode; and a plurality of memory transistors electrically connected to the plurality of memory capacitors. Each memory capacitor includes: a columnar first electrode electrically connected to the memory transistor; a dielectric layer provided on an outer periphery of the first electrode; a second electrode provided on an outer periphery of the dielectric layer and electrically connected to the plate electrode; and an insulating layer provided between the first electrode and the plate electrode and containing a material that is different from a material contained in the dielectric layer.

公开(公告)号：US20230076828A1

公开(公告)日：2023-03-09

申请号：US17693818

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Naoharu SHIMOMURA ,  Nobuyuki UMETSU ,  Tsuyoshi KONDO ,  Yoshihiro UEDA ,  Yasuaki OOTERA ,  Akihito YAMAMOTO ,  Mutsumi OKAJIMA ,  Masaki KADO ,  Tsutomo NAKANISHI ,  Michael Arnaud QUINSAT

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16

Abstract: A magnetic memory of the present embodiment includes an electrode extending along a plane including a first direction and a second direction, a first wiring extending in the first direction, second wirings between the electrode and the first wiring, extending in the second direction and arranged in the first direction, first magnetic members each including a first part electrically connected to the first wiring and a second part electrically connected to the electrode, extending in a third direction, and being positioned between neighboring two of the second wirings when seen from the third direction, and a control circuit. When writing first information to one first magnetic member, the control circuit supplies first current to at least two second wirings positioned on one side of the one first magnetic member in the first direction.

公开(公告)号：US20220406783A1

公开(公告)日：2022-12-22

申请号：US17547710

申请日：2021-12-10

Applicant: Kioxia Corporation

Inventor： Masaharu WADA ,  Mutsumi OKAJIMA

IPC: H01L27/108 ,  H01L29/221 ,  G11C5/02

Abstract: A semiconductor memory device includes a substrate, memory layers, a first wiring disposed at a position closer to the substrate than memory layers or a position farther from the substrate than memory layers, a transistor layer disposed between memory layers and the first wiring, and a second wiring connected to the memory layers and the transistor layer. Each of memory layers includes a memory unit, a first semiconductor layer connected between the memory unit and the second wiring, a first electrode opposed to the first semiconductor layer, a third wiring connected to the first electrode, a second semiconductor layer electrically connected to one end portion of the third wiring, and a second electrode opposed to the second semiconductor layer. The transistor layer includes a third semiconductor layer connected between the first wiring and the second wiring, and a third electrode opposed to the third semiconductor layer.

公开(公告)号：US20220310613A1

公开(公告)日：2022-09-29

申请号：US17472190

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Mutsumi OKAJIMA ,  Yasuaki OOTERA ,  Tsutomu NAKANISHI

IPC: H01L27/108 ,  H01L29/24 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: According to one embodiment, a device includes: a circuit on a first surface of a substrate and including a first contact; an aluminum oxide layer above the substrate in a first direction perpendicular to the first surface; a cell including a capacitor provided in the aluminum oxide layer; a first conductive layer provided between the substrate and the aluminum oxide layer in the first direction and connected to the cell; a first insulating layer between the first conductive layer and the substrate in the first direction; a second insulating layer adjacent to the aluminum oxide layer in a second direction parallel to the first surface and provided above the substrate in the first direction; and a second contact in the second insulating layer and above the first contact in the first direction to connect the cell to the first contact.

公开(公告)号：US20250070024A1

公开(公告)日：2025-02-27

申请号：US18811335

申请日：2024-08-21

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H01L23/528 ,  H01L23/522 ,  H10B53/10 ,  H10B53/20

Abstract: A semiconductor memory device includes a substrate, first semiconductor layers stacked in a first direction intersecting the substrate, a first via wiring extending in the direction and connected to the layers, memory units stacked in the direction and connected to the layers, first gate electrodes stacked in the direction and facing the layers, first wirings stacked in the direction, extending in a second direction intersecting the first direction, and connected to the first electrodes, second semiconductor layers stacked in the first direction and connected to the first electrodes via the first wirings, a second via wiring extending in the first direction and connected to the second layers, and second gate electrodes stacked in the first direction and facing the second layers. The second layers include a different material from the first layers, or a composition ratio of materials of the second layers is different from that of the first layers.