公开(公告)号：US07071960B2

公开(公告)日：2006-07-04

申请号：US10808330

申请日：2004-03-25

申请人： Kiyoshi Toizumi ,  Taisuke Kamimura ,  Toshimitsu Gotoh ,  Tsutomu Yoshimoto ,  Yasuhiro Takai

发明人： Kiyoshi Toizumi ,  Taisuke Kamimura ,  Toshimitsu Gotoh ,  Tsutomu Yoshimoto ,  Yasuhiro Takai

IPC分类号： G03G15/24 ,  G03G15/045 ,  G03G15/047 ,  G03G15/05

CPC分类号： G03G15/05

摘要： Electron generating devices and LED arrays are arranged in a surrounding area of a photosensitive drum. The electron generating devices are located downstream of a cleaner and upstream of a developing unit with respect to a turning direction of the photosensitive drum with a specific gap between the electron generating devices and a surface of the photosensitive drum. The LED arrays are disposed against outer ends of the electron generating devices opposite to inner ends thereof facing the photosensitive drum. When activated by a driving circuit according to image information, individual LED elements of the LED arrays emit light, causing the electron generating devices to emit electrons in a pattern corresponding to the image information. The electrons emitted from the electron generating devices produce more electrons due to an electron avalanche phenomenon before reaching the photosensitive drum, eventually forming an electrostatic latent image on the surface of the photosensitive drum.

摘要翻译： 电子发生器件和LED阵列布置在感光鼓的周围区域中。 电子产生装置相对于感光鼓的转动方向位于清洁器的下游和显影单元的上游，在电子产生装置和感光鼓的表面之间具有特定的间隙。 LED阵列设置在电子产生装置的与端对着感光鼓的内端相对的外端。 当根据图像信息被驱动电路激活时，LED阵列的各个LED元件发光，使得电子发生器件以对应于图像信息的图案发射电子。 从电子产生装置发射的电子在到达感光鼓之前由于电子雪崩现象而产生更多的电子，最终在感光鼓的表面上形成静电潜像。

公开(公告)号：US5041878A

公开(公告)日：1991-08-20

申请号：US456864

申请日：1989-12-27

申请人： Yasuhiro Takai ,  Taisuke Kamimura ,  Yoichi Shimazawa ,  Etsuzi Nukushina

发明人： Yasuhiro Takai ,  Taisuke Kamimura ,  Yoichi Shimazawa ,  Etsuzi Nukushina

IPC分类号： G03G15/01 ,  G03G15/16

CPC分类号： G03G15/0131 ,  G03G15/1605

摘要： In a transfer method of a colored image, the process speed is initially properly set in accordance with the size of a copy paper sheet to be used. The transfer voltage is then changed in accordance with the process speed. After these processes, a colored toner image formed on a photoconductor is first transferred onto an intermediate transfer medium and then further transferred onto the copy paper sheet.

摘要翻译： 在彩色图像的转印方法中，根据要使用的复印纸的尺寸，初始地适当地设定处理速度。 然后根据处理速度改变转印电压。 在这些处理之后，形成在光电导体上的着色调色剂图像首先转印到中间转印介质上，然后进一步转印到复印纸上。

公开(公告)号：US5040028A

公开(公告)日：1991-08-13

申请号：US478823

申请日：1990-02-12

申请人： Taisuke Kamimura ,  Yasuhiro Takai ,  Yoichi Shimazawa ,  Etsuji Nukushina ,  Hideo Matsuda

发明人： Taisuke Kamimura ,  Yasuhiro Takai ,  Yoichi Shimazawa ,  Etsuji Nukushina ,  Hideo Matsuda

IPC分类号： G03G15/16

CPC分类号： G03G15/1605

摘要： A toner transfer device which transfers toner on a photoconductor to an intermediate transfer belt applied on a plurality of rollers, wherein at least part of the surface of the photoconductor moves in an arc while being pressed against the intermediate transfer belt, the toner transfer device comprising: a pair of transfer rollers disposed along the intermediate transfer belt between two of the rollers in such a manner that the part of the surface of the photoconductor which moves in an arc is positioned between the transfer rollers, at least part of each transfer roller being located outside each of two tangents, one of the tangents touching the photoconductor and one of the two rollers, the other tangent touching the photoconductor and the other roller, thereby allowing a certain length of the intermediate transfer belt between the two transfer rollers to be pressed against the part of the surface of the photoconductor moving in an arc; and a means for applying voltage to the transfer rollers, the voltage polarity being opposite to that of the toner.

摘要翻译： 一种调色剂转印装置，其将感光体上的调色剂转印到施加在多个辊上的中间转印带上，其中所述感光体的表面的至少一部分在被压靠在所述中间转印带上的同时移动，所述调色剂转印装置包括 ：沿着中间转印带设置在两个辊之间的一对转印辊，使得以电弧方式移动的感光体的表面的一部分位于转印辊之间，每个转印辊的至少一部分为 位于两个切线的每一个外侧，其中一个切线触摸感光体和两个辊之一，另一个切线接触光电导体和另一个辊，从而允许两个转印辊之间的一定长度的中间转印带被压制 抵抗光电导体表面的弧形运动; 以及用于向转印辊施加电压的装置，其电压极性与调色剂的极性相反。

公开(公告)号：US07669844B2

公开(公告)日：2010-03-02

申请号：US11114081

申请日：2005-04-26

申请人： Toshiki Ohgita ,  Jinichi Nagata ,  Naofumi Okada ,  Kouzou Yamaguchi ,  Hideo Yoshikawa ,  Yasuhiro Takai ,  Syouichirou Yoshiura ,  Tsutomu Yoshimoto

发明人： Toshiki Ohgita ,  Jinichi Nagata ,  Naofumi Okada ,  Kouzou Yamaguchi ,  Hideo Yoshikawa ,  Yasuhiro Takai ,  Syouichirou Yoshiura ,  Tsutomu Yoshimoto

IPC分类号： B65H3/44

CPC分类号： B65H83/025 ,  B65H3/44 ,  B65H2402/10 ,  B65H2405/3311 ,  B65H2511/20 ,  B65H2220/02

摘要： A paper feeder includes a storage section, a feed path, a delivery section, and a receiving section. The storage section is configured to store therein plural sheet members to be fed to a processing apparatus which is operative to perform processing on the sheet members. The feed path allows each of the plural sheet members fed from the storage section to pass therethrough in a feed direction toward the processing apparatus. The delivery section is located most downstream on the feed path in the feed direction. The feed path is open to exterior in the delivery section. The receiving section is located upstream of the feed path in the feed direction for communication with a delivery section of a separate paper feeder having an identical construction with the present paper feeder when the separate paper feeder is disposed upstream of the present paper feeder in the feed direction.

摘要翻译： 供纸器包括存储部分，馈送路径，传送部分和接收部分。 存储部被配置为在其中存储要供给到可对片材部件进行处理的处理装置的多个片状部件。 进给路径允许从存储部分供给的多个片状构件中的每一个在馈送方向上朝向处理装置通过。 输送部分位于馈送方向上最靠近馈送路径的下游。 进料路径在输送段内向外开放。 接收部分在馈送方向上位于馈送路径的上游，以便当分离的供纸器设置在馈送器的上游时，与当前供纸器具有相同结构的单独的供纸器的传送部分连通 方向。

公开(公告)号：US20050236758A1

公开(公告)日：2005-10-27

申请号：US11114081

申请日：2005-04-26

申请人： Toshiki Ohgita ,  Jinichi Nagata ,  Naofumi Okada ,  Kouzou Yamaguchi ,  Hideo Yoshikawa ,  Yasuhiro Takai ,  Syouichirou Yoshiura ,  Tsutomu Yoshimoto

发明人： Toshiki Ohgita ,  Jinichi Nagata ,  Naofumi Okada ,  Kouzou Yamaguchi ,  Hideo Yoshikawa ,  Yasuhiro Takai ,  Syouichirou Yoshiura ,  Tsutomu Yoshimoto

IPC分类号： B65H3/44 ,  B65H5/00

CPC分类号： B65H83/025 ,  B65H3/44 ,  B65H2402/10 ,  B65H2405/3311 ,  B65H2511/20 ,  B65H2220/02

摘要： A paper feeder includes a storage section, a feed path, a delivery section, and a receiving section. The storage section is configured to store therein plural sheet members to be fed to a processing apparatus which is operative to perform processing on the sheet members. The feed path allows each of the plural sheet members fed from the storage section to pass therethrough in a feed direction toward the processing apparatus. The delivery section is located most downstream on the feed path in the feed direction. The feed path is open to exterior in the delivery section. The receiving section is located upstream of the feed path in the feed direction for communication with a delivery section of a separate paper feeder having an identical construction with the present paper feeder when the separate paper feeder is disposed upstream of the present paper feeder in the feed direction.

摘要翻译： 供纸器包括存储部分，馈送路径，传送部分和接收部分。 存储部被配置为在其中存储要供给到可对片材部件进行处理的处理装置的多个片状部件。 进给路径允许从存储部分供给的多个片状构件中的每一个在馈送方向上朝向处理装置通过。 输送部分位于馈送方向上最靠近馈送路径的下游。 进料路径在输送段内向外开放。 接收部分在馈送方向上位于馈送路径的上游，以便当分离的供纸器设置在馈送器的上游时，与当前供纸器具有相同结构的单独的供纸器的传送部分连通 方向。

公开(公告)号：US07944262B2

公开(公告)日：2011-05-17

申请号：US12453652

申请日：2009-05-18

申请人： Koji Kuroki ,  Yasuhiro Takai

发明人： Koji Kuroki ,  Yasuhiro Takai

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.

摘要翻译： 使用至少一个延迟电路形成占空比校正电路，所述至少一个延迟电路由包括三个不同导电类型的晶体管的第一反相器和包括不同导通类型的三个其它晶体管的第二反相器组成，并且其延迟并调整在 前沿/后沿定时，以便基于由检测输出时钟信号的占空比的偏置电路产生的第一或第二偏置电压将其转换为输出时钟信号。 占空比校正电路基于第一偏置电压降低具有高占空比的输出时钟信号的高电平周期。 或者，占空比校正电路基于第二偏置电压增加具有低占空比的输出时钟信号的高电平周期。

公开(公告)号：US07772911B2

公开(公告)日：2010-08-10

申请号：US12208978

申请日：2008-09-11

申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

IPC分类号： G06F1/04

CPC分类号： H03K5/135 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C19/00

摘要： Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal.

摘要翻译： 公开了一种定时控制电路，其接收具有周期T1的第一时钟，以相等间隔彼此间隔开的L个不同相位的一组第二时钟，以及提供给其的选择信号m，n，并产生从 第一时钟信号的上升沿大约为td = m·T1 + n·（T2 / L）的延迟td。 定时控制电路包括粗延迟电路和精细延迟电路。 粗略延迟电路包括用于在激活信号被激活之后对第一时钟信号的上升沿进行计数的计数器，并产生其第一时钟信号的延迟量大约为m·T1的粗略定时信号。 精细延迟电路包括L个并联设置的多相时钟控制延迟电路，通过n·T2 / L延迟由L组第二时钟组的相应时钟对粗略定时信号进行采样的定时， 或者产生延迟脉冲，从而产生精细定时信号。

公开(公告)号：US07734243B2

公开(公告)日：2010-06-08

申请号：US11336901

申请日：2006-01-23

申请人： Toshiki Takiguchi ,  Kouji Wakamoto ,  Tatsuya Inoue ,  Yasuhiro Takai

发明人： Toshiki Takiguchi ,  Kouji Wakamoto ,  Tatsuya Inoue ,  Yasuhiro Takai

IPC分类号： G03G15/00

CPC分类号： G03G15/5008

摘要： In an image forming apparatus of the present invention, an idle roller once stops rotating when a front edge of a sheet conveyed reaches the idle roller. The idle roller restarts rotating at such a timing that a front edge of a toner image on a photoreceptor and a front edge of an image writing position on the sheet are aligned with each other. Then, even if a rear edge of the sheet is still in the idle roller, the idle roller stops rotating when the front edge of the sheet is sandwiched between a transfer roller and the photoreceptor. By carrying out such operations, it is possible to avoid by a very simple way an occurrence of a slip phenomenon that is a phenomenon of slipping of the sheet with respect to the photoreceptor while suppressing a reduction in image quality as much as possible. In addition, it is also possible to surely secure a blank space formed at a rear edge portion of the sheet.

摘要翻译： 在本发明的图像形成装置中，当传送的纸张的前缘到达空转辊时，空转辊一次停止旋转。 空转辊重新开始旋转，使得感光体上的调色剂图像的前边缘和片材上的图像书写位置的前边缘彼此对准。 然后，即使片材的后边缘仍然在空转辊中，当片材的前边缘夹在转印辊和感光体之间时，空转辊停止旋转。 通过进行这种操作，可以通过非常简单的方式避免出现作为尽可能多地抑制图像质量降低的片材相对于感光体的现象的滑动现象。 此外，还可以确保形成在片材的后边缘部分处的空白空间。

公开(公告)号：US07688655B2

公开(公告)日：2010-03-30

申请号：US11747552

申请日：2007-05-11

申请人： Yasuhiro Takai

发明人： Yasuhiro Takai

IPC分类号： G11C29/00

CPC分类号： G11C29/50016 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40622 ,  G11C29/14

摘要： Disclosed is a semiconductor memory device, in which the refresh period of a fail cell or cells is set so as to be shorter than that of the normal cells, comprises a control circuit for exercising control in such a manner that, if, when refreshing the cell of a first address, generated responsive to a refresh command, with an input control signal being of a first value, a second address, differing as to the value of a predetermined bit from the first address, is determined to correspond to a fail cell, based on the information ore-programmed in a refresh redundant ROM, the cell of the second address is refreshed, and also in such a manner that, if, with the input control signal of a second value, the second address, differing as to the value of a predetermined bit from the first address, is determined to correspond to a fail cell, based on the predetermined information, only the cell of the second address is refreshed, without refreshing the cell of the first address, generated responsive to the refresh command.

摘要翻译： 公开了一种半导体存储器件，其中将故障单元或单元的刷新周期设置为短于正常单元的刷新周期，包括用于以这样的方式进行控制的控制电路，即如果在刷新 被确定为响应于刷新命令产生的第一地址的单元，其中输入控制信号是第一值，对于来自第一地址的预定位不同的第二地址被确定为对应于故障单元 基于在刷新冗余ROM中编程的信息，第二地址的单元被刷新，并且还以这样的方式，如果利用第二值的输入控制信号，第二地址不同于 来自第一地址的预定比特的值被确定为对应于故障小区，基于预定信息，仅刷新第二地址的小区，而不刷新第一地址的小区，生成的响应 刷新命令。

公开(公告)号：US20090289676A1

公开(公告)日：2009-11-26

申请号：US12453764

申请日：2009-05-21

申请人： Yasuhiro Takai

发明人： Yasuhiro Takai

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： H03L7/0814 ,  H03K5/13 ,  H03K5/133 ,  H03K2005/00052 ,  H03L7/0818

摘要： A DLL circuit includes a coarse delay adjustment circuit and a fine delay adjustment circuit, which further includes a first fine delay circuit and a second fine delay circuit serving as an interpolation circuit. The coarse delay adjustment circuit delays a reference clock signal by a plurality of delay stages so as to provide the first fine delay circuit with two phase signals having the phase difference of two delay stages, which are then converted into two delay signals having the phase difference of one delay stage. The delay signals are subjected to interpolation, thus producing an output clock signal. Due to a reduction of the phase difference in the first fine delay circuit, it is possible to reduce the minimum operation cycle of the interpolation circuit and to thereby increase the maximum operation frequency of the DLL circuit.

摘要翻译： DLL电路包括粗延迟调整电路和精细延迟调整电路，其还包括作为内插电路的第一精细延迟电路和第二精细延迟电路。 粗延迟调整电路通过多个延迟级对参考时钟信号进行延时，以向第一精细延迟电路提供具有两个延迟级的相位差的两个相位信号，然后将其转换成具有相位差的两个延迟信号 一个延迟阶段。 对延迟信号进行内插，从而产生输出时钟信号。 由于第一精细延迟电路中的相位差减小，可以减小内插电路的最小工作周期，从而增加DLL电路的最大工作频率。