公开(公告)号：US07719921B2

公开(公告)日：2010-05-18

申请号：US12170730

申请日：2008-07-10

申请人： Koji Kuroki ,  Yasuhiro Takai

发明人： Koji Kuroki ,  Yasuhiro Takai

IPC分类号： G11C11/00

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/087

摘要： A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured.

摘要翻译： 占空比检测电路包括放电晶体管，充电晶体管，检测线和检测这些检测线的电位差的比较器电路，还包括根据内部时钟信号控制放电晶体管和充电晶体管的门电路 的偶数周期。 结果，响应于偶数周期的内部时钟信号，检测线被充电和放电。 因此，占空比检测电路可以应用于多相DLL电路，并且可以充分确保出现在检测线中的电位差。

公开(公告)号：US20090289679A1

公开(公告)日：2009-11-26

申请号：US12453652

申请日：2009-05-18

申请人： Koji Kuroki ,  Yasuhiro Takai

发明人： Koji Kuroki ,  Yasuhiro Takai

IPC分类号： H03K3/017 ,  H03H11/26

CPC分类号： H03K5/1565

摘要： A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.

摘要翻译： 使用至少一个延迟电路形成占空比校正电路，所述至少一个延迟电路由包括三个不同导电类型的晶体管的第一反相器和包括不同导通类型的三个其它晶体管的第二反相器组成，并且其延迟并调整在 前沿/后沿定时，以便基于由检测输出时钟信号的占空比的偏置电路产生的第一或第二偏置电压将其转换为输出时钟信号。 占空比校正电路基于第一偏置电压降低具有高占空比的输出时钟信号的高电平周期。 或者，占空比校正电路基于第二偏置电压增加具有低占空比的输出时钟信号的高电平周期。

公开(公告)号：US07710172B2

公开(公告)日：2010-05-04

申请号：US12169972

申请日：2008-07-09

申请人： Koji Kuroki ,  Yasuhiro Takai ,  Hiroki Fujisawa

发明人： Koji Kuroki ,  Yasuhiro Takai ,  Hiroki Fujisawa

IPC分类号： H03L7/06

CPC分类号： H03L7/087 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/10

摘要： A DLL circuit includes a delay line (CDL) (10) that delays a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) (20) that delays the clock signal at a relatively fine adjustment pitch, and phase detecting circuits and counter control circuits that control delay amounts of the delay lines (10, 20). The counter control circuits control the delay line (10) by a linear search method, and control the delay line (20) by a binary search method. As a result, even when the number of bits of the count signal for adjusting the delay line (20) is increased, a delay amount can be determined at a high speed.

摘要翻译： DLL电路包括延迟线（CDL）（10），延迟线（10）以相对粗调的音调延迟时钟信号，延迟线（FDL）（20），以相当精细的调节间距延迟时钟信号;以及相位检测电路 以及控制延迟线（10,20）的延迟量的计数器控制电路。 计数器控制电路通过线性搜索方法控制延迟线（10），并通过二进制搜索方法来控制延迟线（20）。 结果，即使当用于调整延迟线（20）的计数信号的位数增加时，也可以高速地确定延迟量。

公开(公告)号：US07944262B2

公开(公告)日：2011-05-17

申请号：US12453652

申请日：2009-05-18

申请人： Koji Kuroki ,  Yasuhiro Takai

发明人： Koji Kuroki ,  Yasuhiro Takai

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty correction circuit is formed using at least one delay circuit, which is constituted of a first inverter including three transistors of different conduction types and a second inverter including three other transistors of different conduction types and which delays and adjusts an input clock signal at the leading-edge/trailing-edge timing so as to convert it into an output clock signal based on a first or second bias voltage produced by a bias circuit detecting the duty ratio of the output clock signal. The duty correction circuit decreases the high-level period of the output clock signal having a high duty ratio based on the first bias voltage. Alternatively, the duty correction circuit increases the high-level period of the output clock signal having a low duty ratio based on the second bias voltage.

摘要翻译： 使用至少一个延迟电路形成占空比校正电路，所述至少一个延迟电路由包括三个不同导电类型的晶体管的第一反相器和包括不同导通类型的三个其它晶体管的第二反相器组成，并且其延迟并调整在 前沿/后沿定时，以便基于由检测输出时钟信号的占空比的偏置电路产生的第一或第二偏置电压将其转换为输出时钟信号。 占空比校正电路基于第一偏置电压降低具有高占空比的输出时钟信号的高电平周期。 或者，占空比校正电路基于第二偏置电压增加具有低占空比的输出时钟信号的高电平周期。

公开(公告)号：US08120978B2

公开(公告)日：2012-02-21

申请号：US12647277

申请日：2009-12-24

申请人： Koji Kuroki

发明人： Koji Kuroki

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C11/4094

摘要： To provide a semiconductor memory device including: a first clock generation circuit and a second clock generation circuit that generate a first internal clock and a second internal clock, respectively; a latency counter that counts latency synchronously with the first internal clock; and a recovery counter that counts a write recovery period synchronously with the second internal clock. The second clock generation circuit activates the second internal clock when auto-precharge is designated, and deactivates the second internal clock when the auto-precharge is not designated. With this configuration, the recovery counter does not perform any counting operation when an auto-precharge function is not operated, and thus unnecessary power consumption can be prevented.

摘要翻译： 提供一种半导体存储器件，包括：分别产生第一内部时钟和第二内部时钟的第一时钟产生电路和第二时钟产生电路; 延迟计数器，与第一内部时钟同步计数延迟; 以及恢复计数器，其与第二内部时钟同步地计数写恢复周期。 当指定自动预充电时，第二个时钟产生电路激活第二个内部时钟，当未指定自动预充电时，第二个时钟发生电路将激活第二个内部时钟。 通过这种配置，当自动预充电功能不被操作时，恢复计数器不执行任何计数操作，因此可以防止不必要的功率消耗。

公开(公告)号：US20110298290A1

公开(公告)日：2011-12-08

申请号：US13153977

申请日：2011-06-06

申请人： Yoko Ban ,  Koji Kuroki

发明人： Yoko Ban ,  Koji Kuroki

IPC分类号： H02J1/00 ,  G05F1/10

CPC分类号： G11C5/147 ,  Y10T307/696

摘要： In one embodiment, to maintain the operation stability of a semiconductor device even when an external voltage changes. An input signal discrimination unit operates with a power supply potential supplied from a first power supply line VDDI. The input signal discrimination unit compares an input signal VIN with a reference potential Vref. The comparison result is inverted into a signal V0 by an inverter INV1. A power supply sensor circuit monitors the potential of the first power supply line VDDI. If an external potential VDDI falls below a reference potential VX, the power supply sensor circuit turns on a second current source. When the second current source is turned on, an operating current is supplied to a discrimination unit from the second current source as well as a first current source.

摘要翻译： 在一个实施例中，即使当外部电压改变时也保持半导体器件的操作稳定性。 输入信号鉴别单元利用从第一电源线VDDI提供的电源电位进行动作。 输入信号鉴别单元将输入信号VIN与参考电位Vref进行比较。 比较结果由反相器INV1反转成信号V0。 电源传感器电路监视第一电源线VDDI的电位。 如果外部电位VDDI低于参考电位VX，则电源传感器电路接通第二电流源。 当第二电流源接通时，工作电流从第二电流源以及第一电流源提供给鉴别单元。

公开(公告)号：US07580321B2

公开(公告)日：2009-08-25

申请号：US12071198

申请日：2008-02-19

申请人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

发明人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222

摘要： A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

摘要翻译： 本发明的同步半导体存储器件具有：时钟发生器，用于通过对外部时钟进行分频来产生正相和反相时钟;命令解码器，用于解码外部指令并输出命令信号; 延迟设置装置，其能够在外部时钟的预定时钟周期的范围内选择性地设置偶数或奇数等待时间;等待时间计数器，其包括两个计数器电路，用于顺序地移动使用正向和反相位时钟捕获的命令信号 并且能够响应于时钟周期的数量切换信号路径;以及第一和第二控制装置，其通过形成适当的信号路径来控制等于偶数或奇数等待时间的时钟周期的计数。

公开(公告)号：US20070091714A1

公开(公告)日：2007-04-26

申请号：US11583980

申请日：2006-10-20

申请人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

发明人： Hiroki Fujisawa ,  Shuichi Kubouchi ,  Koji Kuroki

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C7/222

摘要： A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency setting means capable of selectively setting an even or odd number latency within a range of a predetermined number of clock cycles of the external clock, a latency counter which includes two counter circuits for sequentially shifting the command signal captured using the normal and reverse phase clock and being capable of switching a signal path in response to the number of clock cycles, and first and second control means which controls counting of the clock cycles equivalent to the even or odd number latency by forming an appropriate signal path.

摘要翻译： 本发明的同步半导体存储器件具有：时钟发生器，用于通过对外部时钟进行分频来产生正相和反相时钟;命令解码器，用于解码外部指令并输出命令信号; 延迟设置装置，其能够在外部时钟的预定时钟周期的范围内选择性地设置偶数或奇数等待时间;等待时间计数器，其包括两个计数器电路，用于顺序地移动使用正向和反相位时钟捕获的命令信号 并且能够响应于时钟周期的数量切换信号路径;以及第一和第二控制装置，其通过形成适当的信号路径来控制等于偶数或奇数等待时间的时钟周期的计数。

公开(公告)号：US09691700B2

公开(公告)日：2017-06-27

申请号：US13137252

申请日：2011-08-01

申请人： Koji Kuroki

发明人： Koji Kuroki

IPC分类号： G11C11/00 ,  H01L23/522 ,  G11C11/4097 ,  H01L27/108

CPC分类号： H01L23/522 ,  G11C11/4097 ,  H01L27/10814 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first signal wiring, a first dummy wiring, and a second dummy wiring. The first signal wiring is configured to be supplied with a first signal potential. The first dummy wiring is insulated from the first wiring. The first dummy wiring is configured to be supplied with a fixed potential. The second dummy wiring is disposed between the first signal wiring and the first dummy wiring. The second dummy wiring is insulated from the first dummy wiring. The second dummy wiring is configured to be supplied with substantially the same potential as the first signal potential.

公开(公告)号：US20110050304A1

公开(公告)日：2011-03-03

申请号：US12871564

申请日：2010-08-30

申请人： Koji Kuroki ,  Ryuji Takishita

发明人： Koji Kuroki ,  Ryuji Takishita

IPC分类号： H03L7/06

CPC分类号： H03L7/085 ,  G11C7/222 ,  H03K5/249 ,  H03L7/0814 ,  H03L7/0816

摘要： In a semiconductor device, there are provided first to third pairs of nMOS transistors between a GND and two sense nodes and first to third pairs of pMOS transistors between the two sense nodes and the power supply. A first internal clock signal and its inverted signal are supplied to gates of the first pair of nMOS transistors and the second pair of nMOS transistors, respectively. Complementary external clock signals are supplied to the gates of the third pairs of nMOS transistors and the third pairs of pMOS transistors. An inverted version of a second internal clock signal and the second internal clock signal are supplied to gates of the first and second pairs of pMOS transistors. The two sense nodes are connected to inputs of a differential amplifier. The output of the differential amplifier is latched by a latch circuit. Also provided an equalizing circuit precharging/equalizing the two sense nodes (FIG. 2).

摘要翻译： 在半导体器件中，在GND和两个感测节点之间提供第一至第三对nMOS晶体管，并且在两个感测节点和电源之间提供第一至第三对pMOS晶体管对。 第一内部时钟信号及其反相信号分别被提供给第一对nMOS晶体管和第二对nMOS晶体管的栅极。 互补的外部时钟信号被提供给第三对nMOS晶体管和第三对pMOS晶体管的栅极。 第二内部时钟信号的反相形式和第二内部时钟信号被提供给第一和第二对pMOS晶体管的栅极。 两个感测节点连接到差分放大器的输入。 差分放大器的输出由锁存电路锁存。 还提供了均衡电路对两个感测节点进行预充电/均衡（图2）。