公开(公告)号：US20090238282A1

公开(公告)日：2009-09-24

申请号：US12380699

申请日：2009-03-03

申请人： Klaus Gaedke ,  Arend Streit

发明人： Klaus Gaedke ,  Arend Streit

IPC分类号： H04N7/26

CPC分类号： H04N19/53 ,  H04N19/102 ,  H04N19/139 ,  H04N19/174 ,  H04N19/176 ,  H04N19/43 ,  H04N19/436 ,  H04N19/61

摘要： The invention is related to the generation of an image data stream and the reconstruction of an image from an image data stream.The method for generating an image data stream comprises the steps of (a) assigning search regions in a reference image to source macro blocks of a current image; (b) determining in the search regions best matches and corresponding residuals and (c) encoding the determined residuals in a data stream. A further feature of the method is related to the fact that the processing order in at least one of the steps (b) and (c) depends on positions of the assigned search regions in the reference image.The variation in the processing order allows for more efficient determination of best matches at encoder side and/or reduced processing requirements at decoder side.

摘要翻译： 本发明涉及图像数据流的生成和从图像数据流重建图像。 用于生成图像数据流的方法包括以下步骤：（a）将参考图像中的搜索区域分配给当前图像的源宏块; （b）在搜索区域中确定最佳匹配和相应的残差，以及（c）在数据流中对所确定的残差进行编码。 该方法的另一个特征在于步骤（b）和（c）中的至少一个中的处理顺序取决于参考图像中所分配的搜索区域的位置。 处理顺序的变化允许更有效地确定编码器侧的最佳匹配和/或解码器侧的减少的处理要求。

公开(公告)号：US08619862B2

公开(公告)日：2013-12-31

申请号：US12380699

申请日：2009-03-03

申请人： Klaus Gaedke ,  Arend Streit

发明人： Klaus Gaedke ,  Arend Streit

IPC分类号： H04B1/66 ,  G06K9/36

CPC分类号： H04N19/53 ,  H04N19/102 ,  H04N19/139 ,  H04N19/174 ,  H04N19/176 ,  H04N19/43 ,  H04N19/436 ,  H04N19/61

摘要： The invention is related to the generation of an image data stream and the reconstruction of an image from an image data stream.The method for generating an image data stream comprises the steps of (a) assigning search regions in a reference image to source macro blocks of a current image; (b) determining in the search regions best matches and corresponding residuals and (c) encoding the determined residuals in a data stream. A further feature of the method is related to the fact that the processing order in at least one of the steps (b) and (c) depends on positions of the assigned search regions in the reference image.The variation in the processing order allows for more efficient determination of best matches at encoder side and/or reduced processing requirements at decoder side.

公开(公告)号：US08107532B2

公开(公告)日：2012-01-31

申请号：US11036663

申请日：2005-01-14

申请人： Klaus Gaedke

发明人： Klaus Gaedke

IPC分类号： H04N7/12

CPC分类号： H04N19/146 ,  H04N19/105 ,  H04N19/176 ,  H04N19/46 ,  H04N19/593 ,  H04N19/60

摘要： Advanced Video Coding uses intra prediction for 4*4 pixel blocks whereby reconstructed samples from adjacent pixel blocks are used to predict a current block. Nine different intra prediction modes are available in AVC. In order to save bits for signalling the prediction modes, a flag and a 3-bit parameter are used. If this flag is set the most probable prediction mode, which is calculated from previous predictions, is used by the encoder and the decoder to reconstruct the actual prediction mode. If the flag is cleared, the 3-bit parameter is sent to select the prediction mode independently. According to the invention, the flag is applied more frequently, based on a prediction error threshold, instead of applying the optimum prediction mode for a current pixel block.

摘要翻译： 高级视频编码对4×4像素块使用帧内预测，​​从而使用来自相邻像素块的重建样本来预测当前块。 AVC中有九种不同的帧内预测模式。 为了保存用于发送预测模式的比特，使用标志和3比特参数。 如果该标志被设置，则由先前预测计算的最可能的预测模式被编码器和解码器用于重建实际的预测模式。 如果标志被清除，则发送3位参数以独立地选择预测模式。 根据本发明，基于预测误差阈值更频繁地应用标志，而不是对当前像素块应用最佳预测模式。

公开(公告)号：US07346073B2

公开(公告)日：2008-03-18

申请号：US10501820

申请日：2003-01-11

申请人： Dieter Haupt ,  Klaus Gaedke ,  Siegfried Schweidler

发明人： Dieter Haupt ,  Klaus Gaedke ,  Siegfried Schweidler

IPC分类号： H04L12/66

CPC分类号： H04L12/40078 ,  H04L12/40091 ,  H04L12/4011 ,  H04L12/64

摘要： The invention deals with a physical layer circuit for the IEEE1394 bus. Considered is a scenario where two clusters of 1394 devices are linked to each other by means of a wireless bridge. The devices of one cluster shall communicate with devices of the other cluster without being bridge aware. Under this scenario there are two different types of 1394 devices existing in each cluster. One device is a bridge portal and will have the bridge functionality. All the other 1394 devices in the cluster will not have the bridge functionality. As the device having the bridge functionality needs to have a specific buffer memory for buffering node-ID packets, usually there are two different types of physical layer circuits required for the different types of 1394 devices. The invention deals with the problem of how it can be realized to use in both different types of 1394 devices the same type of physical layer circuit. The invention solves the problem by means of configuration means in the physical layer circuit. These configuration means enable either to configure the physical layer circuit as a bridge portal physical layer circuit supporting the bridge functionality by buffering said node-ID packets in said buffer memory or else configuring the physical layer circuit as a standard physical layer circuit that disables the buffering of said node-ID packets. The new type of physical layer circuit is pin compatible with a standard physical layer circuit.

摘要翻译： 本发明涉及用于IEEE1394总线的物理层电路。 被认为是两个1394设备的集群通过无线网桥彼此链接的场景。 一个集群的设备应与其他集群的设备进行通信，而不需要桥接。 在这种情况下，每个集群中存在两种不同类型的1394设备。 一个设备是桥接门户，并具有桥接功能。 群集中的所有其他1394设备将不具有桥接功能。 由于具有桥接功能的设备需要具有用于缓冲节点ID分组的特定缓冲存储器，通常存在不同类型的1394设备所需的两种不同类型的物理层电路。 本发明涉及如何实现在不同类型的1394设备中使用相同类型的物理层电路的问题。 本发明通过物理层电路中的配置手段解决了这个问题。 这些配置意味着能够将物理层电路配置为通过将所述节点ID分组缓冲在所述缓冲存储器中来支持桥接功能的桥接门户物理层电路，或者将物理层电路配置为禁用缓冲的标准物理层电路 的所述节点ID分组。 新型物理层电路与标准物理层电路引脚兼容。

公开(公告)号：US07286598B2

公开(公告)日：2007-10-23

申请号：US10854732

申请日：2004-05-26

申请人： Axel Kochale ,  Klaus Gaedke ,  Friedrich Timmermann ,  Oliver Theis

发明人： Axel Kochale ,  Klaus Gaedke ,  Friedrich Timmermann ,  Oliver Theis

IPC分类号： H03K5/159

CPC分类号： G11B20/10212 ,  G11B20/10009 ,  G11B20/1426 ,  H03M5/145 ,  H03M7/46

摘要： A method for bit recovery in an asymmetric data channel, the method comprising the steps of: providing a non-linear equalization filter with two coefficient sets; using the non-linear equalization filter with a first coefficient set for compensating defects of a first type of transition between different storage states; and using the non-linear equalization filter with a second coefficient set for compensating defects of a second type of transition between different storage states.

摘要翻译： 一种用于非对称数据信道中比特恢复的方法，该方法包括以下步骤：提供具有两个系数组的非线性均衡滤波器; 使用具有用于补偿不同存储状态之间的第一类型转换的缺陷的第一系数组的非线性均衡滤波器; 以及使用具有用于补偿不同存储状态之间的第二类型转换的缺陷的第二系数组的非线性均衡滤波器。

公开(公告)号：US20050033894A1

公开(公告)日：2005-02-10

申请号：US10501820

申请日：2003-01-11

申请人： Dieter Haupt ,  Klaus Gaedke ,  Siegfried Schweidler

发明人： Dieter Haupt ,  Klaus Gaedke ,  Siegfried Schweidler

IPC分类号： H04L12/46 ,  H04L12/40 ,  H04L12/64 ,  G06F13/36

CPC分类号： H04L12/40078 ,  H04L12/40091 ,  H04L12/4011 ,  H04L12/64

摘要： The invention deals with a physical layer circuit for the IEEE1394 bus. Considered is a scenario where two clusters of 1394 devices are linked to each other by means of a wireless bridge. The devices of one cluster shall communicate with devices of the other cluster without being bridge aware. Under this scenario there are two different types of 1394 devices existing in each cluster. One device is a bridge portal and will have the bridge functionality. All the other 1394 devices in the cluster will not have the bridge functionality. As the device having the bridge functionality needs to have a specific buffer memory for buffering node-ID packets, usually there are two different types of physical layer circuits required for the different types of 1394 devices. The invention deals with the problem of how it can be realized to use in both different types of 1394 devices the same type of physical layer circuit. The invention solves the problem by means of configuration means in the physical layer circuit. These configuration means enable either to configure the physical layer circuit as a bridge portal physical layer circuit supporting the bridge functionality by buffering said node-ID packets in said buffer memory or else configuring the physical layer circuit as a standard physical layer circuit that disables the buffering of said node-ID packets. The new type of physical layer circuit is pin compatible with a standard physical layer circuit.

摘要翻译： 本发明涉及用于IEEE1394总线的物理层电路。 被认为是两个1394设备的集群通过无线网桥彼此链接的场景。 一个集群的设备应与其他集群的设备进行通信，而不需要桥接。 在这种情况下，每个集群中存在两种不同类型的1394设备。 一个设备是桥接门户，并具有桥接功能。 群集中的所有其他1394设备将不具有桥接功能。 由于具有桥接功能的设备需要具有用于缓冲节点ID分组的特定缓冲存储器，通常存在不同类型的1394设备所需的两种不同类型的物理层电路。 本发明涉及如何实现在不同类型的1394设备中使用相同类型的物理层电路的问题。 本发明通过物理层电路中的配置手段解决了这个问题。 这些配置意味着能够将物理层电路配置为通过将所述节点ID分组缓冲在所述缓冲存储器中来支持桥接功能的桥接门户物理层电路，或者将物理层电路配置为禁用缓冲的标准物理层电路 的所述节点ID分组。 新型物理层电路与标准物理层电路引脚兼容。

公开(公告)号：US07941634B2

公开(公告)日：2011-05-10

申请号：US11985229

申请日：2007-11-14

申请人： Marco Georgi ,  Klaus Gaedke ,  Malte Borsum

发明人： Marco Georgi ,  Klaus Gaedke ,  Malte Borsum

IPC分类号： G06F15/00

CPC分类号： G06T1/60 ,  G06F15/8023

摘要： Specialized image processing circuitry is usually implemented in hardware in a massively parallel way as a single instruction multiple data (SIMD) architecture. The invention prevents long and complicated connection paths between a processing element and the memory subsystem, and improves maximum operating frequency. An optimized architecture for image processing has processing elements that are arranged in a two-dimensional structure, and each processing element has a local storage containing a plurality of reference pixels that are not neighbors in the reference image. Instead, the reference pixels belong to different blocks of the reference image, which may vary for different encoding schemes. Each processing element has a plurality of local first registers for holding the reference image data: one of the first registers holds reference input data of a first search block, and some of the remaining first registers holding reference input data of further search blocks that have specified positions relative to the first search block.

摘要翻译： 专用图像处理电路通常以大规模并行的方式在硬件中实现为单指令多数据（SIMD）架构。 本发明防止处理元件和存储器子系统之间的长而复杂的连接路径，并且提高最大工作频率。 用于图像处理的优化架构具有以二维结构排列的处理元件，并且每个处理元件具有包含在参考图像中不是相邻的多个参考像素的本地存储器。 相反，参考像素属于参考图像的不同块，其可以针对不同的编码方案而变化。 每个处理元件具有用于保持参考图像数据的多个本地第一寄存器：第一寄存器之一保存第一搜索块的参考输入数据，并且其余的第一寄存器中的一些保存了指定的其他搜索块的参考输入数据 相对于第一搜索块的位置。

公开(公告)号：US07656982B2

公开(公告)日：2010-02-02

申请号：US10556835

申请日：2004-04-27

申请人： Klaus Gaedke ,  Friedrich Timmermann ,  Axel Kochale ,  Ralf-Detlef Schaefer ,  Herbert Schütze ,  Marten Kabutz

发明人： Klaus Gaedke ,  Friedrich Timmermann ,  Axel Kochale ,  Ralf-Detlef Schaefer ,  Herbert Schütze ,  Marten Kabutz

IPC分类号： H04L7/04 ,  H04L7/00

CPC分类号： G11B20/10425 ,  G11B20/16 ,  G11B27/3027 ,  G11B2220/2545 ,  G11B2220/2562

摘要： A bit clock recovery apparatus for digital storage readout employing sync frames, where an oversampled readout signal is stored in memory, sync patterns are located in the signal using DSP means, distances of consecutive sync pattern locations are calculated, and bit clock is recovered from these distances and the knowledge about the data framing structure.

摘要翻译： 使用同步帧的数字存储读出的位时钟恢复装置，其中过采样读出信号存储在存储器中，同步模式使用DSP装置位于信号中，计算连续同步模式位置的距离，并从其中恢复位时钟 距离和关于数据框架结构的知识。

公开(公告)号：US07379442B2

公开(公告)日：2008-05-27

申请号：US10491347

申请日：2002-09-19

申请人： Malte Borsum ,  Klaus Gaedke ,  Thomas Brune

发明人： Malte Borsum ,  Klaus Gaedke ,  Thomas Brune

IPC分类号： H04Q7/24 ,  H04L12/28 ,  H04L12/54

CPC分类号： G06F5/10 ,  G06F5/065 ,  H04L47/621 ,  H04L49/90 ,  H04L49/9031 ,  H04L49/9036

摘要： So-called LCH packets are defined in the Hiperlan Type 2 System for wire-free transmission of video and audio data streams. These LCH packets have a length of 54 data bytes. Furthermore, the Hiperlan/2 Standard provides for so-called ARQ messages to be sent back to the transmitter in an SCH packet in a QOS mode (Quality Of Service), in which all the LCH data packets must be confirmed by the receiver. Space for the LCH and SCH data packets must be provided in a buffer store in the Hiperlan/2 interface for each connection that is set up. When there is a possibility of several hundred connections having been set up, separate reservation of memory areas for LCH and SCH packets would involve considerable complexity for the memory organization. The invention proposes that only one common area be reserved for LCH and SCH packets in the buffer store. The section which is provided for each LCH package is of such a size that it corresponds to a value 2n where nε[0, 1, 2, 3, . . . ], and this results in the hardware unit for the address calculation of these data section starts being greatly simplified. However, the area is chosen to be larger than actually required for the buffer storage of one LCH packet. The SCH packets, which likewise need to be buffer-stored, are entered in the unused part of such a section for an LCH packet. This considerably reduces the complexity for memory organization without having to leave a major proportion of the memory unused.

摘要翻译： 在Hiperlan Type 2系统中定义了所谓的LCH分组，用于视频和音频数据流的无线传输。 这些LCH数据包的长度为54个数据字节。 此外，Hiperlan / 2标准提供所谓的ARQ消息，以QOS模式（服务质量）发送回发送方，其中所有LCH数据分组必须由接收机确认。 必须在设置的每个连接的Hiperlan / 2接口的缓冲存储器中提供LCH和SCH数据包的空间。 当存在已经建立了数百个连接的可能性时，用于LCH和SCH分组的存储区域的单独预留将涉及存储器组织的相当大的复杂性。 本发明提出在缓冲存储器中仅为LCH和SCH分组保留一个公共区域。 为每个LCH封装提供的部分具有这样的尺寸，使得其对应于值n 2，其中nepsilon [0,1,2,3，...， 。 。 ]，这导致这些数据部分的地址计算的硬件单元开始被大​​大简化。 然而，该区域被选择为大于实际需要的一个LCH分组的缓冲存储器。 同样需要缓冲存储的SCH分组被输入到用于LCH分组的这种部分的未使用部分中。 这大大降低了内存组织的复杂性，而无需留下大部分内存未使用。

公开(公告)号：US07254662B2

公开(公告)日：2007-08-07

申请号：US10520049

申请日：2003-06-17

申请人： Timothy Heighway ,  Klaus Gaedke ,  Siegfried Schweidler

发明人： Timothy Heighway ,  Klaus Gaedke ,  Siegfried Schweidler

IPC分类号： G06F13/14

CPC分类号： H04L12/40058 ,  H04L12/40078 ,  H04L12/403 ,  H04L29/06 ,  H04L69/18

摘要： According to the IEEE1394 bus protocol, priority is given to isochronous data packets. Data transfer is done in transfer cycles under the control of a cycle master. It depends on the allocated bandwidth for isochronous data how much transport capacity is available in a transfer cycle. To managed the mixed data transfer in one cycle it is specified that the bus nodes not having isochronous data to transfer need to wait with their transmission requests until the end of the isochronous data transfers in the cycle indicated with a sub-action gap. The invention aims to improve the efficiency of data transport for the case that none of the bus nodes need to transfer isochronous data. The data link layer devices according to the invention includes means for checking whether isochronous data is to be transferred and if not they switch over to a no cycle master state, in which the local cycle synchronization events are ignored. The nodes need not wait for a sub-action gap after a local cycle event before drawing asynchronous transmission requests.

摘要翻译： 根据IEEE1394总线协议，给予同步数据包优先。 数据传输在循环主控器的控制下进行。 这取决于等时数据的分配带宽，传输周期中可用的传输容量有多少。 为了在一个周期内管理混合数据传输，规定不具有传输等时数据的总线节点需要等待其传输请求，直到在具有子动作间隙的循环中同步数据传输结束。 本发明的目的是在没有一个总线节点需要传送等时数据的情况下提高数据传输的效率。 根据本发明的数据链路层设备包括用于检查是否要传输同步数据的装置，以及如果不是它们切换到无循环主状态，其中忽略本地周期同步事件。 在绘制异步传输请求之前，节点不需要等待本地周期事件之后的子动作间隙。