公开(公告)号：US20220270676A1

公开(公告)日：2022-08-25

申请号：US17674272

申请日：2022-02-17

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Myung-Su KIM

IPC: G11C11/54 ,  G11C16/04 ,  H01L29/788 ,  H01L29/66

Abstract: Disclosed are a neuromorphic synapse device having an excellent linearity characteristic, and an operating method thereof. According to an embodiment, a neuromorphic synapse device includes a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region, a charge transfer layer region formed on the floating gate region, and a control gate region, which is formed on the charge transfer layer region and which generates a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied, and performs a weight update operation by releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region by using the potential difference.

公开(公告)号：US20200328305A1

公开(公告)日：2020-10-15

申请号：US16607410

申请日：2019-08-20

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Jun Woo SON ,  Jae HUR

IPC: H01L29/78 ,  H01L29/861 ,  H01L21/02 ,  H01L21/3205 ,  H01L27/108

Abstract: A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

公开(公告)号：US20220036168A1

公开(公告)日：2022-02-03

申请号：US17385329

申请日：2021-07-26

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Yang-Kyu CHOI ,  Ji-Man YU

IPC: G06N3/063 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L27/088

Abstract: Disclosed is an ion controllable transistor-based neuromorphic synaptic device used for a memory and a neuromorphic computing in such a manner that a synaptic weight is analogically updated and maintained. The ion controllable transistor-based neuromorphic synaptic device includes a channel area formed on a semiconductor substrate; a source area and a drain area formed at both sides of the channel area, respectively; an interlayer insulating film provided on the channel area; a gate area formed on the interlayer insulating film; and a solid electrolyte layer inserted between the interlayer insulating film and the gate area.

公开(公告)号：US20200303519A1

公开(公告)日：2020-09-24

申请号：US15930804

申请日：2020-05-13

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Byung-Hyun LEE ,  Min-Ho Kang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28

Abstract: Disclosed is a field effect transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels are exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels that are exposed though the hole. Nanowires may include various shapes of current channels that have efficient structures for current path. The cross section of the nanowire can be one of a circle shape, squared shape, rectangular shape, round shape, triangular shape, rhombus shape, eclipse shape, and others.

公开(公告)号：US20190122098A1

公开(公告)日：2019-04-25

申请号：US16169676

申请日：2018-10-24

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu CHOI ,  Jae HUR

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G11C13/00

Abstract: A semiconductor channel based neuromorphic synapse device 1 including a trap-rich layer may be provided that includes: a first to a third semiconductor regions which are formed on a substrate and are sequentially arranged; a word line which is electrically connected to the first semiconductor region; a trap-rich layer which surrounds the second semiconductor region; and a bit line which is electrically connected to the third semiconductor region. When a pulse with positive (+) voltage is applied to the word line, a concentration of electrons emitted from the trap-rich layer to the second semiconductor region increases and a resistance of the second semiconductor region decreases. When a pulse with negative (−) voltage is applied to the word line, a concentration of electrons trapped in the trap-rich layer from the second semiconductor region increases and the resistance of the second semiconductor region increases.

公开(公告)号：US20240047600A1

公开(公告)日：2024-02-08

申请号：US17630463

申请日：2021-12-15

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Joon-Kyu HAN

IPC: H01L31/113 ,  G06N3/067

CPC classification number: H01L31/1136 ,  G06N3/067

Abstract: A transistor for implementing a photo-responsive neuronal device is disclosed. According to one example embodiment, the transistor includes a semiconductor substrate including a hole barrier region or an electron barrier region; a floating body extended in a horizontal direction on the hole barrier region or the electron barrier region; a source region and a drain region formed at both ends of the floating body; a gate insulating film formed on the floating body; and a gate region formed on the gate insulating film.

公开(公告)号：US20230153598A1

公开(公告)日：2023-05-18

申请号：US17976945

申请日：2022-10-31

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Inkyu PARK ,  Joon-Kyu HAN ,  Mingu KANG

IPC: G06N3/065 ,  A61B5/145

CPC classification number: G06N3/065 ,  A61B5/145

Abstract: The present disclosure relates to a gas-responsive neuron module including a resistive gas sensor for sensing gaseous molecules and converting the sensed gaseous molecules into an electrical signal, and a single transistor neuron composed of a source, a drain, and a gate, and a gas sensing system for sensing gas including the same, for implementing a high-integration and low-power neuromorphic electronic nose.

公开(公告)号：US20220270660A1

公开(公告)日：2022-08-25

申请号：US17674301

申请日：2022-02-17

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Myung-Su KIM

IPC: G11C11/404 ,  G11C11/4096

Abstract: Disclosed are a DRAM device capable of storing charges for a long time and an operating method thereof. According to an embodiment, a DRAM device includes a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region, a transition layer region formed on the floating gate region, and a control gate region formed on the transition layer region and generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied and releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region, by generating a transition current due to the potential difference.

公开(公告)号：US20210097380A1

公开(公告)日：2021-04-01

申请号：US17037444

申请日：2020-09-29

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Joon-Kyu HAN ,  Gyeong Jun YUN

IPC: G06N3/063 ,  H01L29/78 ,  H01L29/792 ,  H01L27/1157

Abstract: The present invention relates to a single transistor implementing a neuromorphic system capable of performing neuron and synaptic operations through the single transistor including a floating body layer and a charge storage layer and being implemented by a neuron device and a synaptic device which are co-integrated on the same plane, and the neuromorphic system using the same, and forms the single transistor including a hole barrier material layer formed on a substrate and including a hole barrier material or an electron barrier material, the floating body layer formed on the hole barrier material layer, a source and a drain formed on opposite sides of the floating body layer, a gate insulating layer formed on the floating body layer and including an oxide layer and the charge storage layer, and a gate formed on the gate insulating layer.

公开(公告)号：US20190018986A1

公开(公告)日：2019-01-17

申请号：US16032630

申请日：2018-07-11

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu CHOI ,  Jun-Young PARK

IPC: G06F21/79 ,  G11C13/00 ,  G11C16/34 ,  H01L23/34 ,  H05B3/00

Abstract: The present invention provides a thermal hardware-based data security device that is capable of physically, hardware-wise, and permanently erasing data stored in a memory and of enabling a storage device to be reused, and a method thereof. The thermal hardware-based data security device includes: a memory chip capable of storing data; a heater module which supplies heat to permanently erase the data stored in a memory cell within the memory chip; and a switch module which short-circuits the heater module between a power supply unit and a ground when switched on, and thus, controls the heater module to be operated.