公开(公告)号：US20050017274A1

公开(公告)日：2005-01-27

申请号：US10920389

申请日：2004-08-18

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L21/8242 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06800888B2

公开(公告)日：2004-10-05

申请号：US10759238

申请日：2004-01-20

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L2976

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

公开(公告)号：US06503794B1

公开(公告)日：2003-01-07

申请号：US09381345

申请日：1999-09-20

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster. In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes is formed the first side wall spacer 14 composed of silicon nitride and the second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and are formed connecting portion connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area are formed high density N-type semiconductor areas 16 and 16b, as well as a high density P-type semiconductor area 17 in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 本发明的一个目的是提供一种半导体集成电路的技术，该技术允许每个DRAM存储器单元被细分，以便更高集成度和更快地运行。 在本发明的这种半导体集成电路的制造方法中，首先，通过半导体基板1的主面上的栅极绝缘膜6形成栅电极7，在各栅极电极的侧面 形成由氮化硅构成的第一侧壁隔离物14和由氧化硅构成的第二侧壁隔离物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，以相对于第一侧壁隔板14的自匹配方式打开连接孔19和21，并且形成将导体20连接到位线BL的连接部分。 此外，在N沟道MISFET Qn1和Qn2中以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中形成高密度N型半导体区域16和16b，以及高密度P型 半导体区域17相对于第二侧壁间隔件15以自匹配的方式。

公开(公告)号：US07081649B2

公开(公告)日：2006-07-25

申请号：US10920389

申请日：2004-08-18

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn 1和Q n 2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp 1中，形成高密度N型半导体区域16和16b，以及 高密度P型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US06743673B2

公开(公告)日：2004-06-01

申请号：US10145810

申请日：2002-05-16

申请人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

发明人： Kozo Watanabe ,  Atsushi Ogishima ,  Masahiro Moniwa ,  Syunichi Hashimoto ,  Masayuki Kojima ,  Kiyonori Ohyu ,  Kenichi Kuroda ,  Nozomu Matsuda

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10894 ,  Y10S257/90

摘要： A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL. In addition, in the N channel MISFETs Qn1 and Qn2, and in the P channel MISFET Qp1 in areas other than the DRAM memory cell area, high density N-type semiconductor areas 16 and 16b are formed, as well as a high density P-type semiconductor area 17 is formed in a self-matching manner with respect to the second side wall spacers 15.

摘要翻译： 用于半导体集成电路的技术允许每个DRAM存储单元被细分，以便更高度地集成并且操作更快。 在制造这样的半导体集成电路的方法中，首先，在半导体衬底1的主表面上经由栅极绝缘膜6形成栅电极7，并且在每个栅电极的侧表面上形成第一 由氮化硅构成的侧壁隔板14和由氧化硅构成的第二侧壁间隔物15。 然后，在DRAM存储单元区域中的选择MISFET Qs中，相对于第一侧壁间隔件14以自匹配的方式打开连接孔19和21，并且连接部分形成为将导体20连接到位线BL 。 此外，在N沟道MISFET Qn1和Qn2以及在DRAM存储单元区域以外的区域中的P沟道MISFET Qp1中，形成高密度N型半导体区域16和16b以及高密度P- 型半导体区域17相对于第二侧壁间隔件15以自匹配的方式形成。

公开(公告)号：US5684315A

公开(公告)日：1997-11-04

申请号：US362879

申请日：1994-12-23

申请人： Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Hiroki Soeda ,  Yasuhide Fujioka ,  Nozomu Matsuda ,  Motoko Sawamura

发明人： Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Hiroki Soeda ,  Yasuhide Fujioka ,  Nozomu Matsuda ,  Motoko Sawamura

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/10852 ,  H01L27/10808

摘要： A semiconductor memory device has memory cells provided at intersections between word line conductors and data line conductors. Each of the memory cells includes a cell selecting transistor and an information storage capacitor. The capacitor in each of the memory cells includes a first capacitor component formed over the control electrode of the transistor and a second capacitor component formed over a word line conductor which is adjacent to a word line conductor integral with the control electrode of the transistor. Each of the first and second capacitor components has a common electrode, a storage electrode and a dielectric film sandwiched therebetween, and the storage electrode is at a level higher than the common electrode in each of said first and second capacitor components. The storage electrodes of the first and second capacitor components are electrically connected with each other and with one of the semiconductor regions of the transistor. The other semiconductor region of the transistor is electrically connected with one of the data line conductors. Patterning of the storage electrodes of the first and second capacitor components is preferalbly effected by use of masks of a stripe pattern.

摘要翻译： 半导体存储器件具有在字线导体和数据线导体之间的交叉点处设置的存储单元。 每个存储单元包括单元选择晶体管和信息存储电容器。 每个存储单元中的电容器包括形成在晶体管的控制电极上的第一电容器部件和形成在字线导体上的第二电容器部件，该字线导体与与晶体管的控制电极成一体的字线导体相邻。 第一电容器部件和第二电容器部件中的每一个均具有公共电极，存储电极和夹在其间的电介质膜，并且在所述第一和第二电容器部件的每个中，所述存储电极处于比所述公共电极高的电平。 第一和第二电容器部件的存储电极彼此电连接并且与晶体管的半导体区域中的一个电连接。 晶体管的另一个半导体区域与数据线导体之一电连接。 第一和第二电容器部件的存储电极的图案化优选地通过使用条纹图案的掩模来实现。