公开(公告)号：US11761996B2

公开(公告)日：2023-09-19

申请号：US17732824

申请日：2022-04-29

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G01R19/25 ,  H03K3/037 ,  G05F1/10

CPC classification number: G01R19/2513 ,  G05F1/10 ,  H03K3/037

Abstract: The application provides an apparatus, a system, a detector and a detection method for power supply voltage detection. The apparatus connected to an integrated circuit power supply network comprises: a power supply voltage detector, comprising: N buffers, wherein an input terminal of a first buffer is connected to a clock signal, and output terminals of other buffers are connected to the input terminal of an adjacent buffer; N latch chains, each of which comprises M latches, wherein a clock input terminal of each latch is connected to a clock signal, a D terminal of a first latch of each latch chain is connected to the output terminal of a corresponding buffer, and Q terminals of other latches are connected to the D terminal of an adjacent latch, wherein M and N are positive integers, the VDD terminal of each latch is connected to an area in an integrated circuit power supply network where a power supply voltage is to be detected, and a grounding terminal of each latch is connected to a ground; and a voltage regulation module connected to the Q terminal of each latch and configured to detect data output of each latch to determine a magnitude of a power supply voltage.

公开(公告)号：US20240256450A1

公开(公告)日：2024-08-01

申请号：US18633411

申请日：2024-04-11

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G06F12/0802

CPC classification number: G06F12/0802

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

公开(公告)号：US12013804B2

公开(公告)日：2024-06-18

申请号：US17737527

申请日：2022-05-05

Applicant: Lemon Inc.

Inventor： Yimin Chen ,  Shan Lu ,  Junmou Zhang ,  Chuang Zhang ,  Yuanlin Cheng ,  Jian Wang

IPC: G06F13/42 ,  G06F9/30 ,  G06F13/40 ,  G06F15/173

CPC classification number: G06F13/4282 ,  G06F9/30047 ,  G06F13/4068 ,  G06F15/17368

Abstract: An integrated circuit, and a data processing device and method are provided. The integrated circuit includes a processor circuit and an accelerator circuit. The processor circuit includes a processor, a first data storage section, and a first data input/output interface. The accelerator circuit includes an accelerator and a second data input/output interface. The second data input/output interface is electrically connected to the first data input/output interface, so that the accelerator circuit can perform information interaction with the first data storage section.

公开(公告)号：US11914540B2

公开(公告)日：2024-02-27

申请号：US17737415

申请日：2022-05-05

Applicant: Lemon Inc.

Inventor： Yimin Chen ,  Shan Lu ,  Chuang Zhang ,  Junmou Zhang ,  Yuanlin Cheng ,  Jian Wang

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F2213/40

Abstract: An on-chip integrated circuit, a data processing device and a method are provided. The on-chip integrated circuit includes: a processor circuit and an accelerator circuit. The processor circuit includes a processor and a data storage area, the processor is connected to the data storage area through a first bus in the processor circuit. The accelerator circuit includes an accelerator and a second bus, the accelerator is connected to the second bus, and the second bus is bridged with the first bus corresponding to the data storage area, to perform data interaction between the accelerator and the data storage area, which can reduce the congestion on a bus of the processor and improve the quality of service of the application.

公开(公告)号：US20240310418A1

公开(公告)日：2024-09-19

申请号：US18604457

申请日：2024-03-13

Applicant: Beijing Youzhuju Network Technology Co., Ltd. ,  Lemon Inc.

Inventor： Junyan Guo ,  Weifeng Dong ,  Mingming Zhang ,  Chuang Zhang ,  Junmou Zhang ,  Shan Lu ,  Jian Wang

IPC: G01R25/00 ,  G01R19/165 ,  H03K5/00

CPC classification number: G01R25/005 ,  G01R19/16576 ,  H03K5/00006 ,  H03K2005/00078

Abstract: Embodiments of the present disclosure provide a device and a method for monitoring power supply voltage of an electronic circuit. The device comprising: a voltage regulator configured to process the power supply voltage to generate a predetermined voltage; a critical timing generation module powered by the predetermined voltage and configured to generate a critical timing signal based on an original clock signal and a delay control signal, the critical timing signal being alternately in a first level state and a second level state; a control signal adjustment module configured to adjust the delay control signal based on the critical timing signal, wherein in a case that the critical timing signal is in the first level state, the delay control signal is increased, and in a case that the critical timing signal is in the second level state, the delay control signal is decreased; and a power supply drop sensing module powered by the power supply voltage and configured to generate a drop indication signal based on the original clock signal and the delay control signal, the drop indication signal indicating whether the power supply voltage drops below the predetermined voltage.

公开(公告)号：US11983110B2

公开(公告)日：2024-05-14

申请号：US17850559

申请日：2022-06-27

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

公开(公告)号：US12174232B2

公开(公告)日：2024-12-24

申请号：US17833884

申请日：2022-06-06

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G01R29/02 ,  H03K5/19 ,  H03K19/21

Abstract: A apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a Pth flip-flop flips; a measuring device measuring the pulse signal's width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.

公开(公告)号：US12072356B2

公开(公告)日：2024-08-27

申请号：US17737373

申请日：2022-05-05

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Shan Lu ,  Chuang Zhang ,  Yimin Chen ,  Jian Wang ,  Yuanlin Cheng

IPC: G01R19/10 ,  H03K17/687

CPC classification number: G01R19/10 ,  H03K17/6871

Abstract: A voltage detection circuit and method for an integrated circuit, and an integrated circuit are provided. The voltage detection circuit includes: a first current source, a first branch and a second branch. A current outputted by the first current source is allocated to the first branch and the second branch. The first branch includes a first voltage control current component and a first load connected in series. The second branch includes a current signal detection component and a second load connected in series. A voltage signal to be detected is inputted to a control signal input terminal of the first voltage control current component. The current signal detection component is configured to output, in real time, a preset signal characterizing a second current flowing through the second branch, to determine change of the voltage signal to be detected based on the preset signal.

公开(公告)号：US20230004490A1

公开(公告)日：2023-01-05

申请号：US17850559

申请日：2022-06-27

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G06F12/0802

Abstract: A storage circuit, a chip, a data processing method, and an electronic device are disclosed. The storage circuit includes: an input control circuit and a memory. The input control circuit is configured to: receive n input data and an input control signal; perform first data processing on the n input data based on the input control signal to obtain n intermediate data corresponding to the n input data one by one; and write the n intermediate data and a sign signal corresponding to the n input data into the memory; the memory is configured to store the n intermediate data and the sign signal; different values of the sign signal respectively represent different processing processes of the first data processing, and n is a positive integer.

公开(公告)号：US20230003781A1

公开(公告)日：2023-01-05

申请号：US17833884

申请日：2022-06-06

Applicant: Lemon Inc.

Inventor： Junmou Zhang ,  Dongrong Zhang ,  Shan Lu ,  Jian Wang

IPC: G01R29/02 ,  H03K5/19 ,  H03K19/21

Abstract: A apparatus, method, system and medium are provided. The apparatus includes: a buffer chain, including N first buffers connected end to end, N first AND gates with one input connected to a pulse signal and the other input connected to an output of a corresponding first buffer, and N flip-flops coupled with outputs of respective first AND gates; a path time delay adjustment circuit, with an input receiving a pulse signal, and an output connected to an input terminal of the first buffer; a control apparatus, controlling the time delay produced by the adjustment circuit to be reduced by at least one step from a preset time delay during each adjustment until an output of a Pth flip-flop flips; a measuring device measuring the pulse signal's width according to an output of each flip-flop, the time delay of each first buffer and the time delay of the adjustment circuit.