公开(公告)号：US20250149511A1

公开(公告)日：2025-05-08

申请号：US19018968

申请日：2025-01-13

Applicant: Lodestar Licensing Group LLC

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/482 ,  H01L25/00

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

公开(公告)号：US20240371834A1

公开(公告)日：2024-11-07

申请号：US18776163

申请日：2024-07-17

Applicant: Lodestar Licensing Group LLC

Inventor： Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L25/18

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

公开(公告)号：US20230361083A1

公开(公告)日：2023-11-09

申请号：US18351414

申请日：2023-07-12

Applicant: Lodestar Licensing Group, LLC

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L23/482 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L21/768 ,  H01L25/50 ,  H01L23/4827 ,  H01L23/481

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

公开(公告)号：US20240422967A1

公开(公告)日：2024-12-19

申请号：US18818251

申请日：2024-08-28

Applicant: Lodestar Licensing Group LLC

Inventor： Kunal R. Parekh

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L23/522 ,  H01L23/532 ,  H10B43/27

Abstract: A microelectronic device comprises a memory array region, a control logic region underlying the memory array region, and an interconnect region vertically interposed between the memory array region and the control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically overlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically underlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region comprises control logic devices for the vertically extending strings of memory cells. The interconnect region comprises structures coupling the digit line structures to the control logic devices. Methods of forming a microelectronic device, and memory devices and electronic systems are also described.

公开(公告)号：US20240404976A1

公开(公告)日：2024-12-05

申请号：US18805777

申请日：2024-08-15

Applicant: Lodestar Licensing Group LLC

Inventor： Akira Goda ,  Kunal R. Parekh ,  Aaron S. Yip

IPC: H01L23/00 ,  H01L25/18 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20240015972A1

公开(公告)日：2024-01-11

申请号：US18474080

申请日：2023-09-25

Applicant: Lodestar Licensing Group LLC

Inventor： Haitao Liu ,  Kunal R. Parekh

IPC: H10B43/27 ,  H01L29/47 ,  H01L21/285 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L29/47 ,  H01L21/28537 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.

公开(公告)号：US12199070B2

公开(公告)日：2025-01-14

申请号：US18351414

申请日：2023-07-12

Applicant: Lodestar Licensing Group, LLC

Inventor： Kunal R. Parekh ,  Paolo Tessariol ,  Akira Goda

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/482 ,  H01L25/00

Abstract: A microelectronic device comprises a memory array region, a control logic region, and an additional control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures, and vertically extending strings of memory cells within the stack structure. The control logic region underlies the stack structure and comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The additional control logic region overlies the stack structure and comprises additional control logic devices configured to effectuate an additional portion of the control operations for the vertically extending strings of memory cells. Methods of forming a microelectronic device, and additional microelectronic devices and electronic systems are also described.

公开(公告)号：US12167602B2

公开(公告)日：2024-12-10

申请号：US18196039

申请日：2023-05-11

Applicant: Lodestar Licensing Group LLC

Inventor： Kunal R. Parekh

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20250054935A1

公开(公告)日：2025-02-13

申请号：US18929270

申请日：2024-10-28

Applicant: Lodestar Licensing Group LLC

Inventor： Kunal R. Parekh

IPC: H01L25/00 ,  H10B41/27 ,  H10B43/27

Abstract: A method of forming a microelectronic device comprises forming a source material around substantially an entire periphery of a base material and removing the source material from lateral sides of the base material while maintaining the source material over an upper surface and a lower surface of the base material. Related methods and base structures for microelectronic devices are also described.

公开(公告)号：US20240404880A1

公开(公告)日：2024-12-05

申请号：US18805419

申请日：2024-08-14

Applicant: Lodestar Licensing Group LLC

Inventor： Kyle K. Kirby ,  Kunal R. Parekh ,  Sarah A. Niroumand

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/311 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.