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公开(公告)号：US11121720B2
公开(公告)日：2021-09-14
申请号：US16934002
申请日：2020-07-20
Applicant: MEDIATEK INC.
Inventor： Chan-Hsiang Weng , Hung-Yi Hsieh , Tzu-An Wei , Ting-Yang Wang
Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.
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公开(公告)号：US20190199368A1
公开(公告)日：2019-06-27
申请号：US16190168
申请日：2018-11-14
Applicant: MEDIATEK INC.
Inventor： Chan-Hsiang Weng , Tien-Yu Lo
IPC: H03M3/00
CPC classification number: H03M3/424 , H03M1/06 , H03M1/10 , H03M1/12 , H03M3/30 , H03M3/426 , H03M3/454 , H03M3/456 , H03M3/464
Abstract: A signal processing apparatus has a multi-bit quantizer and a processing circuit. The multi-bit quantizer determines and outputs code segments of a multi-bit output code sequentially. The code segments include a first code segment and a second code segment. The processing circuit generates digital outputs according to the code segments, respectively. The digital outputs include a first digital output derived from a first code segment and a second digital output derived from a second code segment. A first transfer function between the first digital output and the first code segment is different from a second transfer function between the second digital output and the second code segment.
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公开(公告)号：US20170353191A1
公开(公告)日：2017-12-07
申请号：US15586332
申请日：2017-05-04
Applicant: MEDIATEK Inc.
Inventor： Chan-Hsiang Weng , Tien-Yu Lo
IPC: H03M3/00
Abstract: To convert a first stage input to a digital output, a delta-sigma modulator, an analog-to-digital converter and an associated signal conversion method based on an MASH structure are provided. The analog-to-digital converter includes the delta-sigma modulator and a sample and hold circuit. The delta-sigma modulator includes a first signal converter, a second signal converter and a digital cancellation logic. The first signal converter converts the first stage input to a first converted output. The first signal converter shapes a first stage quantization error to generate a second stage input. The first stage input and the second stage input are analog signals. The second signal converter converts the second stage input to a second converted output. The digital cancellation logic generates a digital output according to the first converted output and the second converted output.
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公开(公告)号：US10979069B2
公开(公告)日：2021-04-13
申请号：US16809535
申请日：2020-03-04
Applicant: MEDIATEK INC.
Inventor： Tien-Yu Lo , Chan-Hsiang Weng , Su-Hao Wu
Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.
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公开(公告)号：US20200343899A1
公开(公告)日：2020-10-29
申请号：US16830243
申请日：2020-03-25
Applicant: MEDIATEK INC.
Inventor： Su-Hao Wu , Chan-Hsiang Weng
IPC: H03M1/12
Abstract: The present invention provides a time-interleaved analog-to-digital converter device, wherein the time-interleaved analog-to-digital converter device includes a random number generator, a plurality of ADCs and an output circuit. The random number generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive an analog input signal to generate a plurality of digital signals, respectively, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the digital signals according to the selection signals generated by the ADCs, to generate a digital output signal.
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Patent Agency Ranking
公开(公告)号：US10483947B2
公开(公告)日：2019-11-19
申请号：US16157165
申请日：2018-10-11
Applicant: MEDIATEK Inc.
Inventor： Tien-Yu Lo , Chan-Hsiang Weng , Patrick Cooney , Tsung-Kai Kao , Stacy Ho
Abstract: The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.
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公开(公告)号：US09859914B1
公开(公告)日：2018-01-02
申请号：US15647253
申请日：2017-07-11
Applicant: MEDIATEK INC.
Inventor： Chan-Hsiang Weng , Tien-Yu Lo
CPC classification number: H03M3/426 , H03M1/00 , H03M1/066 , H03M1/12 , H03M3/30 , H03M3/428 , H03M3/436 , H03M3/454
Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter module, a quantizer, a delta-sigma truncator, a digital filter module, and an output circuit. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter module is arranged for filtering the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a first digital signal according to the filtered summation signal. The delta-sigma truncator is arranged for truncating the first digital signal to generate a second digital signal. The digital filter module is arranged for filtering the first digital signal and the second digital signal to generate a filtered first digital signal and a filtered second digital signal, respectively. The output circuit is arranged for generating an output signal according to the filtered first digital signal and the filtered second digital signal.
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公开(公告)号：US10924129B2
公开(公告)日：2021-02-16
申请号：US16830243
申请日：2020-03-25
Applicant: MEDIATEK INC.
Inventor： Su-Hao Wu , Chan-Hsiang Weng
IPC: H03M1/12
Abstract: The present invention provides a time-interleaved analog-to-digital converter device, wherein the time-interleaved analog-to-digital converter device includes a random number generator, a plurality of ADCs and an output circuit. The random number generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive an analog input signal to generate a plurality of digital signals, respectively, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the digital signals according to the selection signals generated by the ADCs, to generate a digital output signal.
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公开(公告)号：US20210044301A1
公开(公告)日：2021-02-11
申请号：US16934002
申请日：2020-07-20
Applicant: MEDIATEK INC.
Inventor： Chan-Hsiang Weng , Hung-Yi Hsieh , Tzu-An Wei , Ting-Yang Wang
Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.
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公开(公告)号：US20200295776A1
公开(公告)日：2020-09-17
申请号：US16809535
申请日：2020-03-04
Applicant: MEDIATEK INC.
Inventor： Tien-Yu Lo , Chan-Hsiang Weng , Su-Hao Wu
IPC: H03M3/00
Abstract: A delta-sigma modulator includes a first combining circuit, a loop filter circuit, a quantizer circuit, a truncator circuit, a first digital-to-analog converter (DAC) circuit, and a compensation circuit. The first combining circuit generates a first analog signal by combining an analog feedback signal and an analog input signal. The loop filter circuit generates a loop-filtered signal according to the first analog signal. The quantizer circuit outputs a first digital signal that is indicative of a digital combination result of at least a truncation error compensation signal and the loop-filtered signal. The truncator circuit performs truncation upon the first digital signal to generate a second digital signal. The first DAC circuit generates the analog feedback signal according to the second digital signal. The compensation circuit generates the truncation error compensation signal according to a truncation error resulting from truncation performed upon the first digital signal.
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