公开(公告)号：US20220283964A1

公开(公告)日：2022-09-08

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G06F12/1045 ,  G06F15/173 ,  G06F9/46 ,  G06F9/455

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US20240411680A1

公开(公告)日：2024-12-12

申请号：US18330007

申请日：2023-06-06

Applicant: Mellanox Technologies, Ltd.

Inventor： Gil Kremer ,  Roee Moyal ,  Igor Voks ,  Liel Peled ,  Eliel Peretz ,  Ariel Shahar

IPC: G06F12/02

Abstract: Apparatuses, systems, and techniques for dynamic memory allocation using a shared free list. A user tag is received, and a hashed user tag is generated. A first reference to an entry in a second data structure is identified in a first data structure using the hashed user tag. The entry includes multiple user tags. Responsive to determining that the multiple user tags do not include the user tag, a memory address is identified in a third data structure. The memory address is removed from the third data structure. Memory is allocated for a user context associated with the user tag at the memory address. The user tag is added to the second data structure.

公开(公告)号：US11762773B2

公开(公告)日：2023-09-19

申请号：US17863453

申请日：2022-07-13

Applicant: Mellanox Technologies, Ltd.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Ariel Shahar ,  Roee Moyal ,  Igor Voks

IPC: G06F12/0813 ,  G06F12/06 ,  G06F9/54 ,  G06F9/50

CPC classification number: G06F12/0813 ,  G06F9/5011 ,  G06F9/544 ,  G06F12/063 ,  G06F2209/508

Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.

公开(公告)号：US20240281292A1

公开(公告)日：2024-08-22

申请号：US18110788

申请日：2023-02-16

Applicant: Mellanox Technologies, Ltd.

Inventor： Natan Manevich ,  Dotan David Levi ,  Wojciech Wasko ,  Shay Aisman ,  Ariel Almog ,  Eliel Peretz ,  Igor Voks

IPC: G06F9/50

CPC classification number: G06F9/5038 ,  G06F9/505

Abstract: A device includes a transceiver coupled to a processing device. The processing device is to determine a first time for executing an operation associated with a work execution agent of a plurality of work execution agent. The processing device is further to receive a latency measurement associated with the work execution agent responsive to transmitting the request. The latency measurement is calculated after executing a previous operation associated with the work execution agent at the device. The processing device is also to modify the first time to a second time for executing the operation responsive to receiving the latency measurement.

公开(公告)号：US20240193106A1

公开(公告)日：2024-06-13

申请号：US18444804

申请日：2024-02-19

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F9/455 ,  G06F9/46 ,  G06F12/1045 ,  G06F13/38 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F13/1668 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/387 ,  G06F13/4221 ,  G06F15/17331 ,  G06F2009/45579

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US11940933B2

公开(公告)日：2024-03-26

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F9/455 ,  G06F9/46 ,  G06F12/1045 ,  G06F13/38 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F13/1668 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/387 ,  G06F13/4221 ,  G06F15/17331 ,  G06F2009/45579

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US20230251899A1

公开(公告)日：2023-08-10

申请号：US17667600

申请日：2022-02-09

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Daniel Marcovitch ,  Natan Manevich ,  Wojciech Wasko ,  Igor Voks

IPC: G06F9/48

CPC classification number: G06F9/4887

Abstract: In one embodiment, a system includes a peripheral device including a hardware clock, and processing circuitry to read a given work request entry stored with a plurality of work request entries in at least one work queue in a memory, the given work request entry including timing data and an operator, the timing data being indicative of a time at which a work request should be executed, retrieve a clock value from the hardware clock, and execute the work request with a workload while execution of the work request is timed responsively to the timing data and the operator and the retrieved clock value.

公开(公告)号：US20220398197A1

公开(公告)日：2022-12-15

申请号：US17863453

申请日：2022-07-13

Applicant: Mellanox Technologies, Ltd.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Ariel Shahar ,  Roee Moyal ,  Igor Voks

IPC: G06F12/0813 ,  G06F12/06 ,  G06F9/54 ,  G06F9/50

Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.

公开(公告)号：US20210406179A1

公开(公告)日：2021-12-30

申请号：US16916153

申请日：2020-06-30

Applicant: Mellanox Technologies, Ltd.

Inventor： Daniel Marcovitch ,  Gil Bloch ,  Richard Graham ,  Ariel Shahar ,  Roee Moyal ,  Igor Voks

IPC: G06F12/0813 ,  G06F12/06 ,  G06F9/50 ,  G06F9/54

Abstract: A network device in a communication network includes a controller and processing circuitry. The controller is configured to manage execution of an operation whose execution depends on inputs from a group of one or more work-request initiators. The processing circuitry is configured to read one or more values, which are set by the work-request initiators in one or more memory locations that are accessible to the work-request initiators and to the network device, and to trigger execution of the operation in response to verifying that the one or more values read from the one or more memory locations indicate that the work-request initiators in the group have provided the respective inputs.