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    Cryptographic data communication apparatus
    4.
    发明授权
    Cryptographic data communication apparatus 有权

    公开(公告)号：US11909856B2

    公开(公告)日：2024-02-20

    申请号：US18076423

    申请日：2022-12-07

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Miriam Menes ,  Noam Bloch ,  Adi Menachem ,  Idan Burstein ,  Ariel Shahar ,  Maxim Fudim

    IPC: H04L9/06 ,  H04L9/32 ,  H04L9/08

    CPC classification number: H04L9/0625 ,  H04L9/0861 ,  H04L9/3247

    Abstract: In one embodiment, an apparatus includes a network interface to receive a sequence of data packets from a remote device responsively to a data transfer request, the received sequence including received data blocks, and packet processing circuitry to read cryptographic parameters from a memory in which the parameters were registered by a processing unit, the cryptographic parameters including an initial cryptographic key and initial value, compute a first cryptographic key responsively to the initial cryptographic key and initial value, cryptographically process a first block responsively to the first cryptographic key, compute an updated value responsively to the initial value and a size of the first block, compute a second cryptographic key responsively to the initial cryptographic key and the updated value, cryptographically process a second block of the received data blocks responsively to the second cryptographic key, and write the cryptographically processed first and second block to the memory.

    Transaction-based reliable transport
    5.
    发明授权
    Transaction-based reliable transport 有权

    公开(公告)号：US11622004B1

    公开(公告)日：2023-04-04

    申请号：US17890385

    申请日：2022-08-18

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Yamin Friedman ,  Idan Burstein ,  Ariel Shahar ,  Diego Crupnicoff ,  Roee Moyal

    IPC: H04L67/1097

    Abstract: A method for communication includes receiving in a network device work requests posted by a host processor to perform a series of communication transactions, including at least a first transaction and a second transaction comprising first and second operations to be executed in a sequential order in response to corresponding first and work requests posted by the host processor. In response to the work requests, data packets are transmitted over a network from the network device to a destination node and corresponding responses are received from the destination node. Based on the received responses, completion of the first operations in the first transaction is reported from the network device to the host processor according to the sequential order, and completion of the second operation in the second transaction is reported from the network device to the host processor regardless of whether the first transaction has been completed.

    Multi-socket network interface controller with consistent transaction ordering
    6.
    发明授权
    Multi-socket network interface controller with consistent transaction ordering 有权

    公开(公告)号：US11620245B2

    公开(公告)日：2023-04-04

    申请号：US17503392

    申请日：2021-10-18

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

    IPC: G06F13/28 ,  G06F3/06

    Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.

    Selective retransmission of packets
    7.
    发明申请
    Selective retransmission of packets 有权

    公开(公告)号：US20220158772A1

    公开(公告)日：2022-05-19

    申请号：US17107990

    申请日：2020-12-01

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Idan Burstein ,  Roee Moyal ,  Ariel Shahar ,  Noam Bloch ,  Ran Koren

    IPC: H04L1/18 ,  G06F15/173

    Abstract: A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.

    Computational accelerator for storage operations
    8.
    发明申请
    Computational accelerator for storage operations 有权

    公开(公告)号：US20210111996A1

    公开(公告)日：2021-04-15

    申请号：US17108002

    申请日：2020-12-01

    Applicant: Mellanox Technologies, Ltd

    Inventor： Boris Pismenny ,  Miriam Menes ,  Idan Burstein ,  Liran Liss ,  Noam Bloch ,  Ariel Shahar

    IPC: H04L12/721 ,  H04L12/717 ,  H04L29/06 ,  G06F11/10

    Abstract: A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.

    Task completion system
    9.
    发明申请
    Task completion system 有权

    公开(公告)号：US20210081236A1

    公开(公告)日：2021-03-18

    申请号：US16571122

    申请日：2019-09-15

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ariel Shahar ,  Roee Moyal

    IPC: G06F9/48

    Abstract: A method including accessing a work control structure (WCS) configured “first-in-first-out” holding work control records (WCRs) each including a field defining work to be carried out and a completion indicator indicating whether the work has completed, and initially set to indicate that the work has not completed: upon fetching a work request (WR) for execution, pushing a WCR corresponding to the WR to the WCS, and: A) inspecting the WCR at a head of the WCS, B) when the completion indicator of the WCR at the head of the WCS indicates that the unit of work associated with the WCR at the head of the WCS has been completed, popping the WCR at the head of the WCS from the WCS, and reporting completion of the WCR at the head of the WCS to a host processor, and C) iteratively performing A, B, and C. Related apparatus and methods are also provided.

    Operation fencing system
    10.
    发明申请
    Operation fencing system 有权

    公开(公告)号：US20210081207A1

    公开(公告)日：2021-03-18

    申请号：US16571220

    申请日：2019-09-16

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ariel Shahar ,  Ahmad Omary

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A method including an executing entity, including fencing dependency circuitry, communicating with physical memory including a work queue (WQ) including a first controlling work request (WR), and a first dependent WR, the first dependent WR including a fencing indication indicating that the first dependent WR should not be executed until the first controlling WR has completed, the fencing dependency circuitry determining that the first dependent WR is ready for execution and checking, based on the fencing indication in the first dependent WR, whether the first controlling WR has completed, and the executing entity executing the first dependent WR only when the first controlling WR has completed. Related apparatus and methods are also provided.

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