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公开(公告)号：US12259832B2
公开(公告)日：2025-03-25
申请号：US18174668
申请日：2023-02-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Tzahi Oved , Achiad Shochat , Liran Liss , Noam Bloch , Aviv Heller , Idan Burstein , Ariel Shahar , Peter Paneah
Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.
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Patent Agency Ranking
公开(公告)号：US20230214341A1
公开(公告)日：2023-07-06
申请号：US18174668
申请日：2023-02-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Tzahi Oved , Achiad Shochat , Liran Liss , Noam Bloch , Aviv Heller , Idan Burstein , Ariel Shahar , Peter Paneah
CPC classification number: G06F13/28 , G06F3/061 , G06F3/0655 , G06F3/0673 , G06F2213/28
Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.
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公开(公告)号：US20220358063A1
公开(公告)日：2022-11-10
申请号：US17503392
申请日：2021-10-18
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Tzahi Oved , Achiad Shochat , Liran Liss , Noam Bloch , Aviv Heller , Idan Burstein , Ariel Shahar , Peter Paneah
Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.
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公开(公告)号：US11620245B2
公开(公告)日：2023-04-04
申请号：US17503392
申请日：2021-10-18
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Tzahi Oved , Achiad Shochat , Liran Liss , Noam Bloch , Aviv Heller , Idan Burstein , Ariel Shahar , Peter Paneah
Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.
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公开(公告)号：US10387358B2
公开(公告)日：2019-08-20
申请号：US15480407
申请日：2017-04-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Tzahi Oved
Abstract: A plurality of Peripheral Component Interconnect Express (PCIe) endpoints of a multi-socket network interface device are attached to a host for exchanging ingress traffic and egress traffic. An operating system of the host includes a bonding/teaming module having a plurality of network interfaces. The bonding/teaming module is configured to select one of the endpoints for the egress traffic. The network interface device has a hardware bond module configured to steer the ingress traffic to designated ones of the endpoints.
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公开(公告)号：US20180232334A1
公开(公告)日：2018-08-16
申请号：US15480407
申请日：2017-04-06
Applicant: Mellanox Technologies, Ltd.
Inventor： Tzahi Oved
CPC classification number: G06F13/4282 , G06F13/4278 , G06F2213/0026 , H04L69/16 , H04L69/22
Abstract: A plurality of Peripheral Component Interconnect Express (PCIe) endpoints of a multi-socket network interface device are attached to a host for exchanging ingress traffic and egress traffic. An operating system of the host includes a bonding/teaming module having a plurality of network interfaces. The bonding/teaming module is configured to select one of the endpoints for the egress traffic. The network interface device has a hardware bond module configured to steer the ingress traffic to designated ones of the endpoints.
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