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    Multi-socket network interface controller with consistent transaction ordering
    1.
    发明申请
    Multi-socket network interface controller with consistent transaction ordering 有权

    公开(公告)号：US20220358063A1

    公开(公告)日：2022-11-10

    申请号：US17503392

    申请日：2021-10-18

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

    IPC: G06F13/28 ,  G06F3/06

    Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.

    Multi-socket network interface controller with consistent transaction ordering
    2.
    发明授权
    Multi-socket network interface controller with consistent transaction ordering 有权

    公开(公告)号：US11620245B2

    公开(公告)日：2023-04-04

    申请号：US17503392

    申请日：2021-10-18

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

    IPC: G06F13/28 ,  G06F3/06

    Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.

    Multi-socket network interface controller with consistent transaction ordering
    3.
    发明授权
    Multi-socket network interface controller with consistent transaction ordering 有权

    公开(公告)号：US12259832B2

    公开(公告)日：2025-03-25

    申请号：US18174668

    申请日：2023-02-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

    IPC: G06F13/28 ,  G06F3/06

    Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

    Dynamically-tuned interrupt moderation
    5.
    发明授权
    Dynamically-tuned interrupt moderation 有权

    公开(公告)号：US10467161B2

    公开(公告)日：2019-11-05

    申请号：US15603493

    申请日：2017-05-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Tal Gilboa ,  Gil Rockah ,  Achiad Shochat ,  Amir Ancel

    IPC: G06F3/06 ,  G06F13/24

    Abstract: Apparatus for communications includes a CPU, a system memory, and a network interface controller (NIC), which is configured to receive incoming data packets from a network, to post the received data packets in a designated queue for delivery to the CPU. The NIC issues interrupts to the CPU in response to the incoming data packets at a rate determined, for the designated queue, in accordance with an interrupt moderation parameter that is set for the queue. During each of a succession of monitoring periods, the CPU measures for the designated queue a current throughput of the incoming data packets and a current rate of interrupts, makes a comparison between the current measured throughput and rate of interrupts to the throughput and rate of interrupts that were measured during a preceding period in the succession, and selects and applies an update to the interrupt moderation parameter responsively to the comparison.

    Dynamically-tuned Interrupt Moderation
    6.
    发明申请
    Dynamically-tuned Interrupt Moderation 审中-公开

    公开(公告)号：US20170344277A1

    公开(公告)日：2017-11-30

    申请号：US15603493

    申请日：2017-05-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Tal Gilboa ,  Gil Rockah ,  Achiad Shochat ,  Amir Ancel

    IPC: G06F3/06 ,  G06F13/24

    CPC classification number: G06F13/24

    Abstract: Apparatus for communications includes a CPU, a system memory, and a network interface controller (NIC), which is configured to receive incoming data packets from a network, to post the received data packets in a designated queue for delivery to the CPU. The NIC issues interrupts to the CPU in response to the incoming data packets at a rate determined, for the designated queue, in accordance with an interrupt moderation parameter that is set for the queue. During each of a succession of monitoring periods, the CPU measures for the designated queue a current throughput of the incoming data packets and a current rate of interrupts, makes a comparison between the current measured throughput and rate of interrupts to the throughput and rate of interrupts that were measured during a preceding period in the succession, and selects and applies an update to the interrupt moderation parameter responsively to the comparison.

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