Automatic assignment of device debug communication pins

    公开(公告)号:US12259705B2

    公开(公告)日:2025-03-25

    申请号:US17530633

    申请日:2021-11-19

    Abstract: An apparatus includes a debugger circuit, debug pins, and a test controller circuit. The test controller circuit is configured to, in a programming mode, determine a subset of the debug pins used in programming the apparatus. The test controller circuit is further configured to save a designation of the subset of the debug pins. The test controller circuit is further configured to, in a test mode subsequent to the programming mode, use the designation to route the subset of the debug pins used in programming the apparatus to the debugger circuit for debug input and output with the server.

    PWM to Control LLC Power Converter
    2.
    发明公开

    公开(公告)号:US20240006982A1

    公开(公告)日:2024-01-04

    申请号:US18217053

    申请日:2023-06-30

    CPC classification number: H02M1/088 H02M3/01 H02M3/33571 H02M1/0009

    Abstract: An inductor-inductor-capacitor (LLC) power converter includes a current input interface to receive a current input indication. The current input indication includes a voltage to represent a current passing through of a primary side of the LLC power converter. The LLC power converter includes voltage input interface to receive a voltage input. The voltage input is to include a representative voltage to be provided from a secondary side of the LLC power converter. The LLC power converter includes a control circuit to generate pulsed-width modulation (PWM) control signals for the LLC power converter. The control circuit is to match an on-time period of a first leg and a second leg of the LLC power converter and based upon the current input indication and the voltage input.

    Temperature compensated clock frequency monitor

    公开(公告)号:US10936004B2

    公开(公告)日:2021-03-02

    申请号:US16143967

    申请日:2018-09-27

    Abstract: A temperature-compensating clock frequency monitor circuit may be provided to detect a clock pulse frequency in an electronic device that may cause erratic or dangerous operation of the device, as a function of an operating temperature of the device. The temperature-compensating clock frequency monitor circuit include a temperature sensor configured to measure a temperature associated with an electronic device, a clock having an operating frequency, and a frequency monitoring system. The frequency monitoring system may be configured to determine the operating frequency of the clock, and based at least on (a) the operating frequency of the clock and (b) the measured temperature associated with the electronic device, generate a corrective action signal to initiate a corrective action associated with the electronic device or a related device. The temperature sensor, clock, and frequency monitoring system may, for example, be provided on a microcontroller.

    Configurable time delays for equalizing pulse width modulation timing
    6.
    发明授权
    Configurable time delays for equalizing pulse width modulation timing 有权
    用于均衡脉宽调制时序的可组态时间延迟

    公开(公告)号:US08866525B2

    公开(公告)日:2014-10-21

    申请号:US13778436

    申请日:2013-02-27

    Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

    Abstract translation: 多个PWM发生器具有用于由其产生的每个PWM控制信号的用户可配置的时间延迟电路。 时间延迟电路被调整,使得每个PWM控制信号同时到达它们相关联的功率晶体管。 这可以通过确定必须经过最长传播时间的PWM控制信号的最大延迟时间,然后将该PWM控制信号的延迟设定为基本为零的延迟来实现。 此后,可以通过从最长传播时间减去每个其它PWM控制信号的传播时间来确定其它PWM控制信号的所有其他延迟时间设置。 从而确保所有的PWM控制信号到达它们各自的功率晶体管控制节点时具有与其离开它们各自的PWM发生器时基本相同的时间关系。

    TIMEBASE PERIPHERAL
    7.
    发明申请
    TIMEBASE PERIPHERAL 有权
    时间外围

    公开(公告)号:US20140040654A1

    公开(公告)日:2014-02-06

    申请号:US13753341

    申请日:2013-01-29

    CPC classification number: G06F1/06 G06F1/04 G06F1/14

    Abstract: A microcontroller has a programmable timebase, wherein the timebase has a trigger input to start a timer or counter of the timebase and wherein the timebase can be configured to operate upon receiving a trigger signal in a first mode to generate a plurality of timer/counter event signals until a reset bit in a control register is set and in a second mode to generate a single timer/counter event signal and wherein the timebase can be configured to operate in a third mode to generate a predefined number of timer/counter event signals, wherein the predefined number is defined by a plurality of bits of a register.

    Abstract translation: 微控制器具有可编程时基,其中所述时基具有触发输入以启动所述时基的定时器或计数器,并且其中所述时基可被配置为在以第一模式接收到触发信号时操作以产生多个定时器/计数器事件 直到控制寄存器中的复位位置1,并且在第二模式中产生单个定时器/计数器事件信号,并且其中该时基可被配置为在第三模式中操作以产生预定数量的定时器/计数器事件信号, 其中预定数量由寄存器的多个位来定义。

    Peripheral special function register with soft-reset disable
    9.
    发明授权
    Peripheral special function register with soft-reset disable 有权
    外设特殊功能寄存器,软复位禁用

    公开(公告)号:US09261931B2

    公开(公告)日:2016-02-16

    申请号:US13753375

    申请日:2013-01-29

    Inventor: Stephen Bowling

    CPC classification number: G06F1/24 G06F1/325

    Abstract: A microcontroller has a plurality of peripherals, and at least one control bit, wherein the control bit controls a reset of at least one peripheral such that in a first mode any type of reset resets the at least one peripheral of said plurality of peripherals and in a second mode only a power supply reset resets the at least one peripheral.

    Abstract translation: 微控制器具有多个外围设备和至少一个控制位,其中控制位控制至少一个外围设备的复位,使得在第一模式中,任何类型的复位复位所述多个外围设备的至少一个外围设备,并且在 只有电源复位的第二模式复位至少一个外设。

    Dithering circuit for serial data transmission
    10.
    发明授权
    Dithering circuit for serial data transmission 有权
    用于串行数据传输的抖动电路

    公开(公告)号:US09054851B2

    公开(公告)日:2015-06-09

    申请号:US14197812

    申请日:2014-03-05

    Abstract: A system for determining a unit time of a serial transmission protocol, wherein the serial transmission protocol defines a unit time (UT) by transmitting a calibration pulse having a predetermined length of N*UT and wherein a receiver is operated by system clock, includes: a clock divider for dividing the system dock by M, wherein M evenly divides N, and a detector for sampling a received data nibble length by using a dithered sampling clock.

    Abstract translation: 一种用于确定串行传输协议的单位时间的系统,其中所述串行传输协议通过发送具有预定长度的N * UT的校准脉冲来定义单位时间(UT),并且其中接收机由系统时钟操作,包括: 用于将系统基座划分为M的时钟分频器,其中M均匀地划分N,以及用于使用抖动采样时钟对接收的数据半字节长度进行采样的检测器。

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