公开(公告)号：US20210358526A1

公开(公告)日：2021-11-18

申请号：US17443673

申请日：2021-07-27

Applicant: Micron Technology, Inc.

Inventor： Yogesh Sharma ,  Atsushi Morishima ,  Yoshihisa Fukushima

IPC: G11C5/06 ,  H05K1/02 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4096

Abstract: Apparatuses and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane.

公开(公告)号：US10165683B2

公开(公告)日：2018-12-25

申请号：US15854598

申请日：2017-12-26

Applicant: Micron Technology, Inc.

Inventor： Atsushi Morishima

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

公开(公告)号：US11107507B2

公开(公告)日：2021-08-31

申请号：US16448541

申请日：2019-06-21

Applicant: Micron Technology, Inc.

Inventor： Yogesh Sharma ,  Atsushi Morishima ,  Yoshihisa Fukushima

IPC: G11C5/06 ,  H05K1/02 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4096

Abstract: Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).

公开(公告)号：US20190098855A1

公开(公告)日：2019-04-04

申请号：US16192673

申请日：2018-11-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Atsushi Morishima

IPC: A01H5/10 ,  C12N15/82 ,  A01H6/54 ,  A01H1/02

CPC classification number: A01H5/10 ,  A01H1/02 ,  A01H6/542 ,  C12N15/8245 ,  C12N15/8247 ,  C12N15/8251 ,  C12N15/8271 ,  C12N15/8274 ,  C12N15/8275 ,  C12N15/8278 ,  C12N15/8279 ,  C12N15/8286 ,  C12N15/8289 ,  H05K1/025 ,  H05K1/114 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/0776 ,  H05K2201/09227 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/0979

Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

公开(公告)号：US10383298B2

公开(公告)日：2019-08-20

申请号：US16192673

申请日：2018-11-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Atsushi Morishima

IPC: A01H5/10 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18 ,  A01H6/54 ,  A01H1/02 ,  C12N15/82

Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

公开(公告)号：US20180192517A1

公开(公告)日：2018-07-05

申请号：US15854598

申请日：2017-12-26

Applicant: Micron Technology, Inc.

Inventor： Atsushi Morishima

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/115 ,  H05K1/025 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/0776 ,  H05K2201/09227 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/0979

Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

公开(公告)号：US09888574B1

公开(公告)日：2018-02-06

申请号：US15399664

申请日：2017-01-05

Applicant: Micron Technology, Inc.

Inventor： Atsushi Morishima

IPC: H05K7/00 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/115 ,  H05K1/025 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/0776 ,  H05K2201/09227 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/0979

Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.