公开(公告)号：US20170285938A1

公开(公告)日：2017-10-05

申请号：US15084979

申请日：2016-03-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G06F12/08 ,  G11C16/32

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.

公开(公告)号：US10802721B2

公开(公告)日：2020-10-13

申请号：US16398646

申请日：2019-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G11C7/10 ,  G06F3/06 ,  G11C16/32 ,  G11C16/26 ,  G06F12/0802 ,  G11C7/22 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US20190258400A1

公开(公告)日：2019-08-22

申请号：US16398646

申请日：2019-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/32 ,  G11C7/10 ,  G11C7/22 ,  G06F12/0802 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal; to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal; and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US20150092499A1

公开(公告)日：2015-04-02

申请号：US14567903

申请日：2014-12-11

Applicant: Micron Technology, Inc.

Inventor： Daesik Song

IPC: G11C16/24 ,  G11C7/12

CPC classification number: G11C16/24 ,  G11C7/12 ,  H03K19/0027 ,  H03K19/018528 ,  H03K19/018585

Abstract: Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.

Abstract translation: 装置和方法可以操作，使得控制晶体管栅极处的数据信号的到达时间以在不同时间切换晶体管，以调制节点上的信号的转换速率。 还描述了另外的实施例。

公开(公告)号：US20180292990A1

公开(公告)日：2018-10-11

申请号：US16006192

申请日：2018-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/32 ,  G11C16/26 ,  G11C7/22 ,  G11C7/10 ,  G06F12/0802

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0215 ,  G06F12/0802 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US10019170B2

公开(公告)日：2018-07-10

申请号：US15084979

申请日：2016-03-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/32 ,  G06F12/0802 ,  G11C7/10 ,  G11C7/22

CPC classification number: G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0215 ,  G06F12/0802 ,  G06F2212/1016 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/7203 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/222 ,  G11C16/26 ,  G11C16/32

Abstract: In an example, a method of operating a memory device to latch data for output from the memory device may include generating a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, generating a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and latching the data in response to the second clock edge of the first clock signal for output from the memory device.

公开(公告)号：US10387048B2

公开(公告)日：2019-08-20

申请号：US16006192

申请日：2018-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric Lee ,  Qiang Tang ,  Ali Feiz Zarrin Ghalam ,  Hoon Choi ,  Daesik Song

IPC: G11C16/32 ,  G06F3/06 ,  G11C16/26 ,  G06F12/0802 ,  G11C7/10 ,  G11C7/22 ,  G06F12/02

Abstract: Memory device including a controller configured to cause the memory device to generate a first clock edge of a first clock signal in response to a first clock edge of a second clock signal, to generate a second, opposite, clock edge of the first clock signal immediately following the first clock edge of the first clock signal in response to a second, opposite, clock edge of the second clock signal immediately following the first clock edge of the second clock signal, and to latch data for output from the memory device in response to the second clock edge of the first clock signal.

公开(公告)号：US09129694B2

公开(公告)日：2015-09-08

申请号：US14567903

申请日：2014-12-11

Applicant: Micron Technology, Inc.

Inventor： Daesik Song

IPC: H03K5/12 ,  G11C16/24 ,  H03K19/00 ,  H03K19/0185 ,  G11C7/12

CPC classification number: G11C16/24 ,  G11C7/12 ,  H03K19/0027 ,  H03K19/018528 ,  H03K19/018585

Abstract: Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.

Abstract translation: 装置和方法可以操作，使得控制晶体管栅极处的数据信号的到达时间以在不同时间切换晶体管，以调制节点上的信号的转换速率。 还描述了另外的实施例。