公开(公告)号：US20200381063A1

公开(公告)日：2020-12-03

申请号：US16987316

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Kalyan Kavalipurapu ,  Michele Piccardi ,  Xiaojiang Guo

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10

Abstract: Disclosed are systems and methods of dynamically calibrating a memory control voltage more accurately. According to disclosed implementations, a memory control voltage such as Vpass or Vwlry may be calibrated during memory operation as a function of the change in slope of total string current, even during increase in the wordline voltage. In one exemplary method, the wordlines are increased in sequence from a start voltage to an end voltage in steps, slope change is measured at every step, the measured slope change is compared against a threshold, and an adjusted memory control voltage is determined as a function of a wordline voltage at which the change in slope reaches the threshold. As such, memory control voltage may be determined and dynamically calibrated with less sensitivity to operating parameters such as temperature, pattern, and/or time of programming.

公开(公告)号：US09443610B1

公开(公告)日：2016-09-13

申请号：US14730372

申请日：2015-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Shigekazu Yamada ,  Allahyar Vahidimowlavi ,  Jae-Kwan Park ,  Cairong Hu ,  Kalyan Kavalipurapu

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G01R31/02

CPC classification number: G11C29/025 ,  G01R31/025 ,  G11C16/0483 ,  G11C2029/1202 ,  G11C2029/5006

Abstract: A system includes a first switch, an amplifier, a second switch, and a capacitor. The first switch is electrically coupled between a first reference voltage and a node. The amplifier has a first input, a second input, and an output, the amplifier to receive a second reference voltage on the first input and a sample voltage on the second input. The second switch is electrically coupled between the output of the amplifier and the second input of the amplifier. The capacitor is electrically coupled between the second input of the amplifier and the node. The first switch and the second switch are closed to initialize the node to the first reference voltage and to initialize the amplifier in unity-gain configuration. The first switch and the second switch are opened to detect a leakage current by sensing a change in the sample voltage.

Abstract translation: 系统包括第一开关，放大器，第二开关和电容器。 第一开关电耦合在第一参考电压和节点之间。 放大器具有第一输入端，第二输入端和输出端，放大器用于在第一输入端接收第二参考电压，并在第二输入端接收采样电压。 第二开关电耦合在放大器的输出端和放大器的第二输入端之间。 电容器电耦合在放大器的第二输入端和节点之间。 关闭第一开关和第二开关以将节点初始化为第一参考电压并以单位增益配置初始化放大器。 打开第一开关和第二开关，通过感测样品电压的变化来检测泄漏电流。

公开(公告)号：US20210210149A1

公开(公告)日：2021-07-08

申请号：US17209012

申请日：2021-03-22

Applicant: Micron Technology, Inc.

Inventor： Kalyan Kavalipurapu ,  Michele Piccardi ,  Xiaojiang Guo

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10

Abstract: Disclosed are systems and methods of dynamically calibrating a memory control voltage more accurately. According to disclosed implementations, a memory control voltage such as Vpass or Vwlrv may be calibrated during memory operation as a function of the change in slope of total string current, even during increase in the wordline voltage. In one exemplary method, the wordlines are increased in sequence from a start voltage to an end voltage in steps, slope change is measured at every step, the measured slope change is compared against a threshold, and an adjusted memory control voltage is determined as a function of a wordline voltage at which the change in slope reaches the threshold. As such, memory control voltage may be determined and dynamically calibrated with less sensitivity to operating parameters such as temperature, pattern, and/or time of programming.

公开(公告)号：US10923199B2

公开(公告)日：2021-02-16

申请号：US16400398

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Michele Piccardi ,  Xiaojiang Guo ,  Kalyan Kavalipurapu

IPC: G11C5/14 ,  G11C16/30 ,  G11C16/26 ,  G05F3/26 ,  H02M3/07

Abstract: An electronic device comprises a multi-chip package including multiple memory dice that include a memory array, charging circuitry, polling circuitry and a control unit. The charging circuitry is configured to perform one or more memory events in a high current mode using a high current level or in a low current mode using a lower current level. The polling circuitry is configured to poll a power status node common to the multiple memory dice to determine availability of the high current mode. The control unit is configured to operate the charging circuitry in the high current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is available, and operate the charging circuitry in the low current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is unavailable.

公开(公告)号：US20200350026A1

公开(公告)日：2020-11-05

申请号：US16400398

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： Michele Piccardi ,  Xiaojiang Guo ,  Kalyan Kavalipurapu

IPC: G11C16/30 ,  H02M3/07 ,  G05F3/26 ,  G11C16/26

Abstract: An electronic device comprises a multi-chip package including multiple memory dice that include a memory array, charging circuitry, polling circuitry and a control unit. The charging circuitry is configured to perform one or more memory events in a high current mode using a high current level or in a low current mode using a lower current level. The polling circuitry is configured to poll a power status node common to the multiple memory dice to determine availability of the high current mode. The control unit is configured to operate the charging circuitry in the high current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is available, and operate the charging circuitry in the low current mode to perform the one or more memory events when the polling circuitry indicates that the high current mode is unavailable.

公开(公告)号：US09143132B2

公开(公告)日：2015-09-22

申请号：US14174555

申请日：2014-02-06

Applicant: Micron Technology, Inc.

Inventor： William Kammerer ,  Kalyan Kavalipurapu

IPC: H03K19/003 ,  H03K19/0185 ,  H04L25/02 ,  H03K19/00 ,  G11C16/04

CPC classification number: H03K19/018514 ,  G11C16/04 ,  H03K19/0005 ,  H04L25/0278

Abstract: Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described.

Abstract translation: 描述包括用于互补信号的终止的装置以及用于终止互补信号的方法。 一种这样的装置包括终端晶体管，其包括被配置为接收第一互补信号的第一节点和被配置为接收第二互补信号的第二节点。 调节电路可以产生调节电压以使终端晶体管以基本上恒定的电阻导通。 在一种这样的方法中，在终端晶体管的漏极处接收第一互补信号，并且在终止晶体管的源极处接收第二互补信号。 当端接晶体管导通时，补偿信号的能量可以被吸收。 还描述了另外的实施例。

公开(公告)号：US11315642B2

公开(公告)日：2022-04-26

申请号：US17209012

申请日：2021-03-22

Applicant: Micron Technology, Inc.

Inventor： Kalyan Kavalipurapu ,  Michele Piccardi ,  Xiaojiang Guo

IPC: G11C16/32 ,  G11C11/00 ,  G11C16/30 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56

Abstract: Disclosed are systems and methods of dynamically calibrating a memory control voltage more accurately. According to disclosed implementations, a memory control voltage such as Vpass or Vwlrv may be calibrated during memory operation as a function of the change in slope of total string current, even during increase in the wordline voltage. In one exemplary method, the wordlines are increased in sequence from a start voltage to an end voltage in steps, slope change is measured at every step, the measured slope change is compared against a threshold, and an adjusted memory control voltage is determined as a function of a wordline voltage at which the change in slope reaches the threshold. As such, memory control voltage may be determined and dynamically calibrated with less sensitivity to operating parameters such as temperature, pattern, and/or time of programming.

公开(公告)号：US10984875B2

公开(公告)日：2021-04-20

申请号：US16987316

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Kalyan Kavalipurapu ,  Michele Piccardi ,  Xiaojiang Guo

IPC: G11C11/56 ,  G11C16/32 ,  G11C16/30 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10

Abstract: Disclosed are systems and methods of dynamically calibrating a memory control voltage more accurately. According to disclosed implementations, a memory control voltage such as Vpass or Vwlrv may be calibrated during memory operation as a function of the change in slope of total string current, even during increase in the wordline voltage. In one exemplary method, the wordlines are increased in sequence from a start voltage to an end voltage in steps, slope change is measured at every step, the measured slope change is compared against a threshold, and an adjusted memory control voltage is determined as a function of a wordline voltage at which the change in slope reaches the threshold. As such, memory control voltage may be determined and dynamically calibrated with less sensitivity to operating parameters such as temperature, pattern, and/or time of programming.

公开(公告)号：US10741260B1

公开(公告)日：2020-08-11

申请号：US16424448

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Kalyan Kavalipurapu ,  Michele Piccardi ,  Xiaojiang Guo

IPC: G11C11/56 ,  G11C16/32 ,  G11C16/30 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10

Abstract: Disclosed are systems and methods of dynamically calibrating a memory control voltage more accurately. According to disclosed implementations, a memory control voltage such as Vpass or Vwlrv may be calibrated during memory operation as a function of the change in slope of total string current, even during increase in the wordline voltage. In one exemplary method, the wordlines are increased in sequence from a start voltage to an end voltage in steps, slope change is measured at every step, the measured slope change is compared against a threshold, and an adjusted memory control voltage is determined as a function of a wordline voltage at which the change in slope reaches the threshold. As such, memory control voltage may be determined and dynamically calibrated with less sensitivity to operating parameters such as temperature, pattern, and/or time of programming.

公开(公告)号：US20140153334A1

公开(公告)日：2014-06-05

申请号：US14174555

申请日：2014-02-06

Applicant: Micron Technology, Inc.

Inventor： William Kammerer ,  Kalyan Kavalipurapu

IPC: H03K19/0185 ,  G11C16/04

CPC classification number: H03K19/018514 ,  G11C16/04 ,  H03K19/0005 ,  H04L25/0278

Abstract: Apparatuses including termination for complementary signals are described, along with methods for terminating complementary signals. One such apparatus includes a termination transistor including a first node configured to receive a first complementary signal and a second node configured to receive a second complementary signal. A regulation circuit can generate a regulated voltage to render the termination transistor conductive with a substantially constant resistance. In one such method, a first complementary signal is received at a drain of a termination transistor and a second complementary signal is received at a source of the termination transistor. Energy of the complimentary signals can be absorbed when the termination transistor is rendered conductive. Additional embodiments are also described.

Abstract translation: 描述包括用于互补信号的终止的装置以及用于终止互补信号的方法。 一种这样的装置包括终端晶体管，其包括被配置为接收第一互补信号的第一节点和被配置为接收第二互补信号的第二节点。 调节电路可以产生调节电压以使终端晶体管以基本上恒定的电阻导通。 在一种这样的方法中，在终端晶体管的漏极处接收第一互补信号，并且在终止晶体管的源极处接收第二互补信号。 当端接晶体管导通时，可以吸收互补信号的能量。 还描述了另外的实施例。