公开(公告)号：US20190206485A1

公开(公告)日：2019-07-04

申请号：US16298313

申请日：2019-03-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10

Abstract: Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.

公开(公告)号：US09858991B2

公开(公告)日：2018-01-02

申请号：US15287956

申请日：2016-10-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/0408 ,  G11C16/0458 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/562 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5648

Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programing the first memory cell to the first level. After programing the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programing the second memory cell to the second level.

公开(公告)号：US20210241832A1

公开(公告)日：2021-08-05

申请号：US17238482

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： Allahyar Vahidimowlavi ,  Kalyan C. Kavalipurapu

IPC: G11C16/08 ,  G11C8/14 ,  G11C5/06 ,  G11C16/12 ,  G11C16/04 ,  G11C8/08

Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) upon the selected wordline reaching the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.

公开(公告)号：US20200185033A1

公开(公告)日：2020-06-11

申请号：US16752981

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Allahyar Vahidimowlavi ,  Kalyan C. Kavalipurapu

IPC: G11C16/08 ,  G11C8/08 ,  G11C16/04 ,  G11C16/12 ,  G11C5/06 ,  G11C8/14

Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.

公开(公告)号：US20150262657A1

公开(公告)日：2015-09-17

申请号：US14725749

申请日：2015-05-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/0408 ,  G11C16/0458 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/562 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5648

Abstract: Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used.

Abstract translation: 公开了两部分编程存储器以减少电池干扰。 在至少一个实施例中，数据以两个或更多个编程脉冲序列编程，其中首先编程需要更高编程电压的数据。 在每个编程序列期间，禁止当前未选择编程的数据。 可以使用重叠电平和/或电压范围。

公开(公告)号：US10249365B2

公开(公告)日：2019-04-02

申请号：US15831718

申请日：2017-12-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.

公开(公告)号：US09443610B1

公开(公告)日：2016-09-13

申请号：US14730372

申请日：2015-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Feng Pan ,  Shigekazu Yamada ,  Allahyar Vahidimowlavi ,  Jae-Kwan Park ,  Cairong Hu ,  Kalyan Kavalipurapu

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G01R31/02

CPC classification number: G11C29/025 ,  G01R31/025 ,  G11C16/0483 ,  G11C2029/1202 ,  G11C2029/5006

Abstract: A system includes a first switch, an amplifier, a second switch, and a capacitor. The first switch is electrically coupled between a first reference voltage and a node. The amplifier has a first input, a second input, and an output, the amplifier to receive a second reference voltage on the first input and a sample voltage on the second input. The second switch is electrically coupled between the output of the amplifier and the second input of the amplifier. The capacitor is electrically coupled between the second input of the amplifier and the node. The first switch and the second switch are closed to initialize the node to the first reference voltage and to initialize the amplifier in unity-gain configuration. The first switch and the second switch are opened to detect a leakage current by sensing a change in the sample voltage.

Abstract translation: 系统包括第一开关，放大器，第二开关和电容器。 第一开关电耦合在第一参考电压和节点之间。 放大器具有第一输入端，第二输入端和输出端，放大器用于在第一输入端接收第二参考电压，并在第二输入端接收采样电压。 第二开关电耦合在放大器的输出端和放大器的第二输入端之间。 电容器电耦合在放大器的第二输入端和节点之间。 关闭第一开关和第二开关以将节点初始化为第一参考电压并以单位增益配置初始化放大器。 打开第一开关和第二开关，通过感测样品电压的变化来检测泄漏电流。

公开(公告)号：US11222699B2

公开(公告)日：2022-01-11

申请号：US17010334

申请日：2020-09-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to inhibit memory cells of a first subset of memory cells from programming during each programming pulse of a first plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of a second plurality of programming pulses, inhibit memory cells of a second subset of memory cells from programming during each programming pulse of the second plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of the first plurality of programming pulses, and enable memory cells of a third subset of memory cells for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse of the second plurality of programming pulses.

公开(公告)号：US10546641B1

公开(公告)日：2020-01-28

申请号：US16214007

申请日：2018-12-07

Applicant: Micron Technology, Inc.

Inventor： Allahyar Vahidimowlavi ,  Kalyan C. Kavalipurapu

IPC: G11C16/08 ,  G11C8/14 ,  G11C5/06 ,  G11C16/12 ,  G11C16/04 ,  G11C8/08

Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.

公开(公告)号：US20170025170A1

公开(公告)日：2017-01-26

申请号：US15287956

申请日：2016-10-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vishal Sarin ,  Allahyar Vahidimowlavi

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/0408 ,  G11C16/0458 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/562 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5648

Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programing the first memory cell to the first level. After programing the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programing the second memory cell to the second level.

Abstract translation: 使用第一编程电压范围内的第一组编程脉冲将第一存储单元编程为第一电平。 在将第一存储器单元编程到第一级时，禁止要编程到小于第一级的第二级的第二存储器单元。 在将第一存储器单元编程到第一电平之后，使用第二编程电压范围内的第二组编程脉冲将第二存储单元编程到第二电平，其中第一编程电压范围与第二编程电压范围重叠。 在将第二存储器单元编程到第二级时，禁止编程到第一级的第一存储器单元。