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    HIGH-VOLTAGE SHIFTER WITH REDUCED TRANSISTOR DEGRADATION
    4.
    发明申请
    HIGH-VOLTAGE SHIFTER WITH REDUCED TRANSISTOR DEGRADATION 有权

    公开(公告)号：US20210249084A1

    公开(公告)日：2021-08-12

    申请号：US17240358

    申请日：2021-04-26

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C16/12 ,  G11C16/04 ,  G11C29/02 ,  G11C16/10 ,  G11C16/14

    Abstract: Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second H V control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.

    High-voltage shifter with reduced transistor degradation
    5.
    发明授权
    High-voltage shifter with reduced transistor degradation 有权

    公开(公告)号：US10998050B2

    公开(公告)日：2021-05-04

    申请号：US16813273

    申请日：2020-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C29/02 ,  G11C16/12

    Abstract: Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.

    HIGH-VOLTAGE SHIFTER WITH DEGRADATION COMPENSATION
    6.
    发明申请
    HIGH-VOLTAGE SHIFTER WITH DEGRADATION COMPENSATION 审中-公开

    公开(公告)号：US20200243145A1

    公开(公告)日：2020-07-30

    申请号：US16259610

    申请日：2019-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C16/30 ,  G11C16/16 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C5/14 ,  G11C5/06

    Abstract: Discussed herein are systems and methods for compensating degradation of a transistor in a high-voltage (HV) shifter configured to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises a group of memory cells, and a HV shifter circuit including a signal transfer circuit and a compensator circuit. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The compensator circuit can provide a control signal to the signal transfer circuit by coupling a support voltage higher than a supply voltage (Vcc) to the signal transfer circuit for a specified time period to compensate for degradation of the P-channel transistor. The transferred high voltage is used to charge the access line to selectively read, program, or erase memory cells.

    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS
    7.
    发明申请
    APPARATUSES AND METHODS TO CONTROL BODY POTENTIAL IN MEMORY OPERATIONS 有权
    用于控制存储器操作中的身体潜力的装置和方法

    公开(公告)号：US20150287472A1

    公开(公告)日：2015-10-08

    申请号：US14746416

    申请日：2015-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

    IPC: G11C16/32 ,  G11C16/04

    CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

    Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

    Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于装置的不同级别中的存储器单元和耦合到存储单元串的数据线。 存储单元串包括与存储单元相关联的柱体。 这种装置中的至少一个可以包括被配置为在存储器单元之间存储信息到存储器单元中的模块和/或确定存储器单元中存储在存储单元中的信息的值。 该模块还可以被配置为向数据线和/或源施加具有正值的电压以控制身体的电位。 描述其他实施例。

    LEAKAGE MEASUREMENT SYSTEMS
    8.
    发明申请
    LEAKAGE MEASUREMENT SYSTEMS 有权
    泄漏测量系统

    公开(公告)号：US20150109867A1

    公开(公告)日：2015-04-23

    申请号：US14584584

    申请日：2014-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C7/06

    CPC classification number: G11C7/06 ,  G11C16/00 ,  G11C16/0483 ,  G11C29/025 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2029/5006

    Abstract: Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a supply voltage. The boosted voltage may be generated by charge pump circuitry. Examples of leakage measurement systems described herein may be included in memory devices.

    Abstract translation: 所描述的示例包括泄漏测量系统和用于测量升压电压的字线与电源电压下的字线之间的漏电流的方法。 升压电压可能由电荷泵电路产生。 这里描述的泄漏测量系统的示例可以包括在存储器设备中。

    APPARATUSES, INTEGRATED CIRCUITS, AND METHODS FOR MEASURING LEAKAGE CURRENT
    9.
    发明申请
    APPARATUSES, INTEGRATED CIRCUITS, AND METHODS FOR MEASURING LEAKAGE CURRENT 有权
    装置，集成电路和测量泄漏电流的方法

    公开(公告)号：US20150029802A1

    公开(公告)日：2015-01-29

    申请号：US14514218

    申请日：2014-10-14

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada

    IPC: G11C29/02

    CPC classification number: G11C29/025 ,  G11C8/08 ,  G11C2029/1202 ,  G11C2029/5006

    Abstract: Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first voltage, and a measurement node is charged to a second voltage, the second voltage being less than the first voltage. The measurement node is proportionally coupled to the word line. A voltage on the measurement node is compared with a reference voltage. A signal is generated, the signal being indicative of the comparison. Whether a leakage current of the word line is acceptable or not can be determined based on the signal.

    Abstract translation: 公开了用于测量泄漏电流的方法，装置和集成电路。 在一个这样的示例方法中，字线被充电到第一电压，并且测量节点被充电到第二电压，第二电压小于第一电压。 测量节点按比例耦合到字线。 将测量节点上的电压与参考电压进行比较。 产生信号，该信号表示比较。 可以基于该信号来确定字线的泄漏电流是否可接受。

    Select gate programming in a memory device
    10.
    发明授权
    Select gate programming in a memory device 有权
    在存储设备中选择门编程

    公开(公告)号：US08873297B2

    公开(公告)日：2014-10-28

    申请号：US14018926

    申请日：2013-09-05

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada ,  Aaron Yip

    IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/34

    CPC classification number: G11C16/102 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

    Abstract: Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.

    Abstract translation: 公开了用于编程选择门，存储器件和存储器系统的方法。 在一种用于编程的方法中，程序禁止电压从源传输到未选位线。 在未被选择的位线和要被编程禁止的选定位线之间的位线对位线电容将所选择的禁止位线的位线电压升高到目标抑制电压。 在一个实施例中，可以在多个禁止步骤中增加所选择的禁止位线上的电压，由此在编程的未选择栅极的编程期间可以使用一个，两个或所有步骤。

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