公开(公告)号：US20140205056A1

公开(公告)日：2014-07-24

申请号：US13748256

申请日：2013-01-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tadashi Yamamoto

IPC: G11C19/00

CPC classification number: G11C19/287 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/12 ,  G11C15/00 ,  G11C19/00 ,  G11C2029/4402 ,  H01L25/0657 ,  H01L27/10 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.

Abstract translation: 各种实施例包括将唯一的设备标识符值分配给堆叠包装中的可寻址设备的装置。 在一个实施例中，公开了一种包括具有至少两个可寻址装置的堆叠封装的装置。 每个可寻址设备包括数据输入和开关路径电路，耦合到数据输入和开关路径电路的移位寄存器，以及可以分配唯一设备标识符值的单个通孔（TSV）。 单个TSV耦合到数据输入和开关路径电路以及在至少两个可寻址装置中相邻的TSV之间。 描述附加的装置，系统和方法。

公开(公告)号：US20140052878A1

公开(公告)日：2014-02-20

申请号：US14064717

申请日：2013-10-28

Applicant: Micron Technology, Inc.

Inventor： Yutaka Ito ,  Tadashi Yamamoto

IPC: G06F1/32 ,  G06F3/06

CPC classification number: G06F1/3228 ,  G06F1/3203 ,  G06F3/0659

Abstract: Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 公开了在存储器内操作以执行内部命令，在传送期间暂停命令的执行以及在传送周期之后执行外部命令的装置，系统和方法。 公开了附加装置，系统和方法。

公开(公告)号：US09558844B2

公开(公告)日：2017-01-31

申请号：US14553579

申请日：2014-11-25

Applicant: Micron Technology, Inc.

Inventor： Tadashi Yamamoto

IPC: G11C7/00 ,  G11C19/28 ,  G11C19/00 ,  G11C7/10 ,  G11C8/12 ,  G11C7/22 ,  G11C15/00 ,  H01L27/10 ,  H01L25/065 ,  G11C29/44

CPC classification number: G11C19/287 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/12 ,  G11C15/00 ,  G11C19/00 ,  G11C2029/4402 ,  H01L25/0657 ,  H01L27/10 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.

Abstract translation: 各种实施例包括将唯一的设备标识符值分配给堆叠包装中的可寻址设备的装置。 在一个实施例中，公开了一种包括具有至少两个可寻址装置的堆叠封装的装置。 每个可寻址设备包括数据输入和开关路径电路，耦合到数据输入和开关路径电路的移位寄存器，以及可以分配唯一设备标识符值的单个通孔（TSV）。 单个TSV耦合到数据输入和开关路径电路以及在至少两个可寻址装置中相邻的TSV之间。 描述附加的装置，系统和方法。

公开(公告)号：US20150085968A1

公开(公告)日：2015-03-26

申请号：US14553579

申请日：2014-11-25

Applicant: Micron Technology, Inc.

Inventor： Tadashi Yamamoto

IPC: G11C19/28 ,  H01L25/065 ,  H01L27/10

CPC classification number: G11C19/287 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/12 ,  G11C15/00 ,  G11C19/00 ,  G11C2029/4402 ,  H01L25/0657 ,  H01L27/10 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.

Abstract translation: 各种实施例包括将唯一的设备标识符值分配给堆叠包装中的可寻址设备的装置。 在一个实施例中，公开了一种包括具有至少两个可寻址装置的堆叠封装的装置。 每个可寻址设备包括数据输入和开关路径电路，耦合到数据输入和开关路径电路的移位寄存器，以及可以分配唯一设备标识符值的单个通孔（TSV）。 单个TSV耦合到数据输入和开关路径电路以及在至少两个可寻址装置中相邻的TSV之间。 描述附加的装置，系统和方法。

公开(公告)号：US08902680B2

公开(公告)日：2014-12-02

申请号：US13748256

申请日：2013-01-23

Applicant: Micron Technology, Inc.

Inventor： Tadashi Yamamoto

IPC: G11C7/00 ,  G11C19/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/12

CPC classification number: G11C19/287 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/12 ,  G11C15/00 ,  G11C19/00 ,  G11C2029/4402 ,  H01L25/0657 ,  H01L27/10 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.

Abstract translation: 各种实施例包括将唯一的设备标识符值分配给堆叠包装中的可寻址设备的装置。 在一个实施例中，公开了一种包括具有至少两个可寻址装置的堆叠封装的装置。 每个可寻址设备包括数据输入和开关路径电路，耦合到数据输入和开关路径电路的移位寄存器，以及可以分配唯一设备标识符值的单个通孔（TSV）。 单个TSV耦合到数据输入和开关路径电路以及在至少两个可寻址装置中相邻的TSV之间。 描述附加的装置，系统和方法。

公开(公告)号：US08819298B2

公开(公告)日：2014-08-26

申请号：US14064717

申请日：2013-10-28

Applicant: Micron Technology, Inc.

Inventor： Yutaka Ito ,  Tadashi Yamamoto

IPC: G06F3/00 ,  G11C7/00 ,  G11C8/18

CPC classification number: G06F1/3228 ,  G06F1/3203 ,  G06F3/0659

Abstract: Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 公开了在存储器内操作以执行内部命令，在传送期间暂停命令的执行以及在传送周期之后执行外部命令的装置，系统和方法。 公开了附加装置，系统和方法。

公开(公告)号：US09466348B2

公开(公告)日：2016-10-11

申请号：US14565822

申请日：2014-12-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jacob Robert Anderson ,  Kang-Yong Kim ,  Tadashi Yamamoto ,  Zer Liang ,  Huy Vo

IPC: G11C7/00 ,  G11C8/12 ,  G11C7/10 ,  G06F13/42

CPC classification number: G11C8/12 ,  G06F13/4234 ,  G11C7/00 ,  G11C7/10 ,  Y02D10/14 ,  Y02D10/151

Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.

Abstract translation: 公开了包含命令解码器，芯片使能和信号截断电路的存储器。 一个这样的命令解码器电路可以包括命令解码器逻辑，其被配置为接收命令信号，并且响应于具有活动状态的片选信号而将解码的命令输出到互连总线。 解码器电路还可以基于接收到具有无效状态的片选信号来防止到互连总线的耦合命令。 具有控制逻辑的芯片使能电路被配置为接收芯片选择信号，并且响应于接收到有效命令而将芯片选择信号提供给互连总线。 芯片使能电路还可以基于无效命令信号的接收，防止从芯片使能信号将互连芯片选择信号耦合到互连总线。 信号截断电路可用于缩短和/或移位芯片选择信号以增加定时裕度并提高存储器执行命令的可靠性。