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公开(公告)号：US08862863B2
公开(公告)日：2014-10-14
申请号：US13951008
申请日：2013-07-25
Applicant: Micron Technology, Inc.
Inventor： Kang-Yong Kim , Jacob Robert Anderson , Huy Vo
CPC classification number: G11C7/20 , G11C29/003 , G11C29/32 , G11C29/50012 , G11C2029/0407 , H01L25/0657
Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.
Abstract translation: 公开了设备，主 - 从检测电路，存储器和方法。 一种这样的方法包括执行主检测阶段，在此期间，将存储器组中的存储器单元确定为主存储器单元，在每个存储器单元处确定其相对于其他存储器单元的位置，以及在每个存储器单元处确定其位于 存储器组基于从属存储器单元的总数及其相对于其他存储器单元的位置。
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Patent Agency Ranking
公开(公告)号：US20240212731A1
公开(公告)日：2024-06-27
申请号：US18391380
申请日：2023-12-20
Applicant: Micron Technology, Inc.
Inventor： Jacob Robert Anderson
Abstract: Methods, systems, and devices for memory array circuit arrangement are described. A memory device may include a memory subarray, which may include a complementary metal oxide semiconductor (CMOS) circuitry under array (CuA) circuitry area and a word line driver region (e.g., word line driver circuitry) or a digit line driver region (e.g., digit line driver circuitry, sense amplifier circuitry multiplexed with the digit line driver circuitry). The memory subarray may include a first interconnect extending in a first and traversing at least a first portion of the CuA circuitry area of the memory subarray. The first interconnect may be coupled with the first portion of the CuA circuitry area and a first interconnection layer. Additionally, each memory subarray may include a second interconnect extending in a second direction and traversing at least a second portion of the CuA circuitry area of the memory subarray.
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公开(公告)号：US09881658B2
公开(公告)日：2018-01-30
申请号：US14505740
申请日：2014-10-03
Applicant: Micron Technology, Inc.
Inventor： Kang-Yong Kim , Jacob Robert Anderson , Huy Vo
CPC classification number: G11C7/20 , G11C29/003 , G11C29/32 , G11C29/50012 , G11C2029/0407 , H01L25/0657
Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.
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公开(公告)号：US20150058656A1
公开(公告)日：2015-02-26
申请号：US14505740
申请日：2014-10-03
Applicant: Micron Technology, Inc.
Inventor： Kang-Yong Kim , Jacob Robert Anderson , Huy Vo
CPC classification number: G11C7/20 , G11C29/003 , G11C29/32 , G11C29/50012 , G11C2029/0407 , H01L25/0657
Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.
Abstract translation: 公开了设备，主 - 从检测电路，存储器和方法。 一种这样的方法包括执行主检测阶段，在此期间，将存储器组中的存储器单元确定为主存储器单元，在每个存储器单元处确定其相对于其他存储器单元的位置，以及在每个存储器单元处确定其位于 存储器组基于从属存储器单元的总数及其相对于其他存储器单元的位置。
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公开(公告)号：US09466348B2
公开(公告)日：2016-10-11
申请号：US14565822
申请日：2014-12-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jacob Robert Anderson , Kang-Yong Kim , Tadashi Yamamoto , Zer Liang , Huy Vo
CPC classification number: G11C8/12 , G06F13/4234 , G11C7/00 , G11C7/10 , Y02D10/14 , Y02D10/151
Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.
Abstract translation: 公开了包含命令解码器，芯片使能和信号截断电路的存储器。 一个这样的命令解码器电路可以包括命令解码器逻辑，其被配置为接收命令信号，并且响应于具有活动状态的片选信号而将解码的命令输出到互连总线。 解码器电路还可以基于接收到具有无效状态的片选信号来防止到互连总线的耦合命令。 具有控制逻辑的芯片使能电路被配置为接收芯片选择信号，并且响应于接收到有效命令而将芯片选择信号提供给互连总线。 芯片使能电路还可以基于无效命令信号的接收，防止从芯片使能信号将互连芯片选择信号耦合到互连总线。 信号截断电路可用于缩短和/或移位芯片选择信号以增加定时裕度并提高存储器执行命令的可靠性。
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公开(公告)号：US20130311818A1
公开(公告)日：2013-11-21
申请号：US13951008
申请日：2013-07-25
Applicant: Micron Technology, Inc.
Inventor： Kang-Yong Kim , Jacob Robert Anderson , Huy Vo
IPC: G06F1/08
CPC classification number: G11C7/20 , G11C29/003 , G11C29/32 , G11C29/50012 , G11C2029/0407 , H01L25/0657
Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.
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