公开(公告)号：US20240339152A1

公开(公告)日：2024-10-10

申请号：US18627960

申请日：2024-04-05

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim ,  Wonjun Choi

IPC: G11C11/4091 ,  G11C11/4078 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4078 ,  G11C11/4096

Abstract: Apparatuses and techniques for implementing a data sense amplifier circuit with a hybrid architecture. With the hybrid architecture, the data sense amplifier circuit includes a first set of amplifiers that are shared by multiple banks and includes a second set of amplifiers with multiple subsets dedicated to different banks. The bank-shared amplifiers support memory operations (e.g., a read operation) across multiple banks. Each amplifier within the first set of amplifiers is coupled to at least two banks. The bank-specific amplifiers support usage-based disturbance mitigation for a corresponding bank. Each amplifier within the second set of amplifiers is coupled to one of the multiple banks. The bank-shared amplifiers enable the data sense amplifier circuit to have a smaller footprint while the bank-specific amplifiers enable the data sense amplifier circuit to support usage-based disturbance mitigation and avoid conflicts associated with some sequences of commands.

公开(公告)号：US20250021875A1

公开(公告)日：2025-01-16

申请号：US18755355

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Wonjun Choi ,  Hyunyoo Lee ,  Smruti Subhash Jhaveri

IPC: G06N20/00

Abstract: Test data associated with a command bus training (CBT) can be separately received at interconnected memory dice. Feedback data that are outputted from the multiple interconnected memory dice in response to the test data can be randomly combined such that combined feedback data is returned as if the feedback data were sent from a single memory die. This provides a flexible and scalable architecture that can accommodate a range of memory densities (e.g., a number of memory dice that are interconnected).

公开(公告)号：US20240338126A1

公开(公告)日：2024-10-10

申请号：US18627859

申请日：2024-04-05

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Yang Lu ,  Wonjun Choi ,  Mark Kalei Hadrick

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0673

Abstract: Apparatuses and techniques for implementing collision avoidance for bank-shared circuitry that supports usage-based disturbance mitigation are described. A memory device includes bank-shared circuitry coupled to multiple banks. The bank-shared circuitry can support usage-based disturbance mitigation. By using the bank-shared circuitry to service multiple banks, the memory device can have a smaller footprint and can be cheaper to manufacture compared to other memory devices with circuitry dedicated for each bank. To avoid conflicts associated with some sequences of commands that may relate to a same bank or different banks and utilize the bank-shared circuitry, the memory controller applies an appropriate timing offset (or delay) between commands. The timing offset allows the memory device time to finish utilizing the bank-shared circuitry for usage-based disturbance mitigation prior to utilizing the bank-shared circuitry in accordance with a subsequent command.

公开(公告)号：US20220406358A1

公开(公告)日：2022-12-22

申请号：US17350305

申请日：2021-06-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroshi Akamatsu ,  Wonjun Choi ,  Jacob Rice ,  Kenji Yoshida

IPC: G11C11/4076 ,  G11C11/408

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

公开(公告)号：US20250111872A1

公开(公告)日：2025-04-03

申请号：US18747740

申请日：2024-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wonjun Choi ,  Hyun Yoo Lee

IPC: G11C11/406

Abstract: Apparatuses, systems, and methods for refresh rate register adjustment based on a targeted refresh queue. A memory includes a temperature sensor which measures a temperature of the memory. The memory also includes a targeted refresh queue which stores identified aggressor addresses. A value of a refresh rate register is set based on both the measured temperature and the number of addresses in the queue. A controller of the memory reads the value of the refresh rate register and provides a refresh signal with timing based on the refresh rate register. In some embodiments, a ratio of targeted and normal refresh operations is adjusted based on how many addresses are in the targeted refresh queue.

公开(公告)号：US20240274720A1

公开(公告)日：2024-08-15

申请号：US18642326

申请日：2024-04-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroshi Akamatsu ,  Wonjun Choi ,  Jacob Rice ,  Kenji Yoshida

IPC: H01L29/786 ,  H01L29/20 ,  H01L29/66 ,  H01L29/737 ,  H01L29/74 ,  H10B12/00 ,  H10B53/30

CPC classification number: H01L29/78618 ,  H01L28/56 ,  H01L28/57 ,  H01L28/60 ,  H01L28/65 ,  H01L29/2003 ,  H01L29/6684 ,  H01L29/7375 ,  H01L29/7408 ,  H01L29/7869 ,  H10B53/30 ,  H10B12/312 ,  H10B12/36

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

公开(公告)号：US11967356B2

公开(公告)日：2024-04-23

申请号：US17350305

申请日：2021-06-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hiroshi Akamatsu ,  Wonjun Choi ,  Jacob Rice ,  Kenji Yoshida

IPC: G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G11C11/4087

Abstract: An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.