公开(公告)号：US20180082622A1

公开(公告)日：2018-03-22

申请号：US15711817

申请日：2017-09-21

申请人： Hopil Bae ,  Mahdi Farrokh Baroughi ,  Mohammad B. Vahid Far ,  Xiang Lu ,  Bo Yang ,  Derek K. Shaeffer ,  Henry C. Jen

发明人： Hopil Bae ,  Mahdi Farrokh Baroughi ,  Mohammad B. Vahid Far ,  Xiang Lu ,  Bo Yang ,  Derek K. Shaeffer ,  Henry C. Jen

IPC分类号： G09G3/00 ,  G09G3/36

CPC分类号： G09G3/006 ,  G09G3/32 ,  G09G3/367 ,  G09G2310/0275

摘要： The present techniques are capable of identifying and pinpointing defective microdrivers and/or row/column drivers either before or after any μLEDs have been placed on the display. Using the architectures described herein, test data may be delivered in a parallel fashion to the drivers from support circuitry, such as a timing controller and/or a main board, and outputs based on the test data may be similarly delivered back to the support circuitry do determine which drivers are defective. This yields access to the output of every microdriver and row drier, thus enabling the identification of specific defective elements.

公开(公告)号：US20180090059A1

公开(公告)日：2018-03-29

申请号：US15713140

申请日：2017-09-22

申请人： Mahdi Farrokh Baroughi ,  Bo Yang ,  Xiang Lu ,  Hopil Bae

发明人： Mahdi Farrokh Baroughi ,  Bo Yang ,  Xiang Lu ,  Hopil Bae

IPC分类号： G09G3/32 ,  G09G3/00

CPC分类号： G09G3/32 ,  G09G3/006 ,  G09G2300/0452 ,  G09G2330/08 ,  G09G2330/12

摘要： Methods and systems for testing a display having an array of microdrivers arranged in multiple of rows and columns including setting a testing mode of a microdriver of the array of microdrivers using multiple pins of the microdriver that are used in scanning or operation modes of the microdriver. The microdriver is configured to light one or more connected micro light emitting diode pixels coupled to the microdriver during the testing mode. Testing also includes operating the microdriver in the testing mode and determining functionality of the one or more connected micro light emitting diode pixels or the microdriver based on the testing mode.

公开(公告)号：US20140063958A1

公开(公告)日：2014-03-06

申请号：US13600792

申请日：2012-08-31

申请人： Yi He ,  Xiang Lu ,  Albert Bergemont

发明人： Yi He ,  Xiang Lu ,  Albert Bergemont

IPC分类号： G11C16/10

CPC分类号： G11C16/0408 ,  G11C2216/10

摘要： N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.

摘要翻译： 具有N-导电类型衬底，N导电类型衬底中的第一和第二P导电类型阱的N沟道多时间可编程存储器件，形成在第一P导电型阱中的N导电型源极和漏极区 源极和漏极区域被沟道区域分隔，N导电型衬底上的氧化物层; 以及在N导电类型衬底中在沟道区域上延伸超过第二P导电类型的浮栅，多时间可编程存储单元可通过热电子注入进行编程，并可通过热空穴注入进行擦除。

公开(公告)号：US6027988A

公开(公告)日：2000-02-22

申请号：US915132

申请日：1997-08-20

申请人： Nathan W. Cheung ,  Xiang Lu ,  Chenming Hu

发明人： Nathan W. Cheung ,  Xiang Lu ,  Chenming Hu

IPC分类号： H01L21/223 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324

CPC分类号： H01L21/2236 ,  H01L21/76251 ,  Y10S438/977

摘要： A technique for fabricating substrates such as a silicon-on-insulator substrate using a plasma immersion ion implantation ("PIII") system 10. The technique includes a method, which has a step of providing a substrate 2100. Ions are implanted 2109 into a surface of the substrate to a first desired depth to provide a first distribution of the ions using a plasma immersion ion implantation system 10. The implanted ions define a first thickness of material 2101 above the implant. Global energy is then increased of the substrate to initiate a cleaving action, where the cleaving action is sufficient to completely free the thickness of material from a remaining portion of the substrate. By way of the PIII system, the ions are introduced into the substrate in an efficient and cost effective manner.

公开(公告)号：US06757494B2

公开(公告)日：2004-06-29

申请号：US09747697

申请日：2000-12-22

申请人： Xiang Lu ,  Alan R Briggs ,  Kevin Warbrick

发明人： Xiang Lu ,  Alan R Briggs ,  Kevin Warbrick

IPC分类号： H04B1000

CPC分类号： H04L45/62 ,  H04Q11/0062 ,  H04Q2011/0073

摘要： In a photonic network, signals are degraded by passing through amplifiers. A maximum number of amplifiers may be traversed before regeneration is necessary. Regeneration (typically carried out in an optical cross-connect) involves relatively expensive hardware and is to be avoided if possible. An algorithm is set out which operates in two stages. In a first stage untenable paths are rejected and in a second stage the shortest path analyzes are carried out which maximizes the number of amplifiers interspersed between regenerative nodes thereby to minimize the use of regenerative nodes but ensures that all paths have regenerative nodes spaced at no more than a maximum interval of non-regenerative nodes.

摘要翻译： 在光子网络中，信号通过放大器衰减。 在需要再生之前可以遍历最大数量的放大器。 再生（通常在光学交叉连接中进行）涉及相对昂贵的硬件，并且如果可能的话将被避免。 设置了两个阶段的算法。 在第一阶段，不可靠的路径被拒绝，并且在第二阶段中，进行最短路径分析，其使再生节点之间散布的放大器的数量最大化，从而最小化再生节点的使用，但是确保所有路径具有不再具有间隔的再生节点 超过非再生节点的最大间隔。

公开(公告)号：US08975685B2

公开(公告)日：2015-03-10

申请号：US13600792

申请日：2012-08-31

申请人： Yi He ,  Xiang Lu ,  Albert Bergemont

发明人： Yi He ,  Xiang Lu ,  Albert Bergemont

IPC分类号： H01L29/788

CPC分类号： G11C16/0408 ,  G11C2216/10

摘要： N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.

摘要翻译： 具有N-导电类型衬底，N导电类型衬底中的第一和第二P导电类型阱的N沟道多时间可编程存储器件，形成在第一P导电型阱中的N导电型源极和漏极区 源极和漏极区域被沟道区域分隔，N导电型衬底上的氧化物层; 以及在N导电类型衬底中在沟道区域上延伸超过第二P导电类型的浮栅，多时间可编程存储单元可通过热电子注入进行编程，并可通过热空穴注入进行擦除。

公开(公告)号：US08796767B1

公开(公告)日：2014-08-05

申请号：US13153932

申请日：2011-06-06

申请人： Xiang Lu ,  Albert Bergemont

发明人： Xiang Lu ,  Albert Bergemont

IPC分类号： H01L21/70

CPC分类号： H01L21/28035 ,  H01L21/28105 ,  H01L21/70 ,  H01L27/0623 ,  H01L27/0705 ,  H01L29/4983

摘要： Techniques are described to form a low-noise, high-gain semiconductor device. In one or more implementations, the device includes a substrate including a first dopant material having a concentration ranging from about 1×1010/cm3 to about 1×1019/cm3. The substrate also includes at least two active regions formed proximate to a surface of the substrate. The at least two active regions include a second dopant material, which is different than the first dopant material. The device further includes a gate structure formed over the surface of the substrate between the active regions. The gate structure includes a doped polycrystalline layer and an oxide layer formed over the surface between the surface and the doped polycrystalline layer. The doped polycrystalline layer includes the first dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3.

摘要翻译： 描述技术以形成低噪声，高增益半导体器件。 在一个或多个实施方式中，该器件包括包含浓度范围为约1×10 10 / cm 3至约1×10 19 / cm 3的第一掺杂剂材料的衬底。 衬底还包括靠近衬底的表面形成的至少两个有源区。 所述至少两个有源区包括与第一掺杂剂材料不同的第二掺杂剂材料。 该器件还包括形成在有源区域之间的衬底表面上的栅极结构。 栅极结构包括掺杂多晶层和在表面和掺杂多晶层之间的表面上形成的氧化物层。 掺杂多晶层包括浓度范围为约1×1019 / cm3至约1×1021 / cm3的第一掺杂剂材料。

公开(公告)号：US06981065B1

公开(公告)日：2005-12-27

申请号：US09573239

申请日：2000-05-18

申请人： Xiang Lu

发明人： Xiang Lu

IPC分类号： G06F15/16 ,  G06F15/173 ,  H04J3/08 ,  H04L12/28 ,  H04L12/56

CPC分类号： H04J3/085 ,  H04J2203/0053 ,  H04J2203/0055 ,  H04J2203/0067 ,  H04L12/2852 ,  H04L12/2856 ,  H04L12/2874 ,  H04L45/04 ,  H04L45/26 ,  H04L45/48 ,  H04L45/507

摘要： A method of provisioning a connection across a SONET/SDU network formed from multiple sub-networks comprises: determining a model of the entire network, the model indicating the connections between all sub-networks, and representing each sub-network as a single unit; calculating a route between the sub-networks containing the first and second nodes using the model; passing the signals along the determined route, and determining the route between nodes within each sub-network locally within the respective sub-network. This method enables a simplified model of the network to be stored in each node of the network, so that a route calculation can take place at the sending node. The specific route through the network is determined as the signal passes through the network, as the specific path through individual sub-networks is determined locally. Thus, each node only needs to be capable of calculating a general route using the simplified model of the whole network and also capable of calculating a specific route through the sub-network of the node itself.

摘要翻译： 一种通过由多个子网形成的SONET / SDU网络提供连接的方法包括：确定整个网络的模型，所述模型指示所有子网络之间的连接，并将每个子网络表示为单个单元; 使用模型计算包含第一和第二节点的子网络之间的路由; 沿着确定的路由传递信号，以及确定各个子网内本地节点之间的路由。 该方法使网络的简化模型能够存储在网络的每个节点中，从而可以在发送节点进行路由计算。 当通过本地确定通过各个子网络的特定路径时，通过网络的特定路由被确定为信号通过网络。 因此，每个节点仅需要能够使用整个网络的简化模型计算一般路由，并且还能够计算通过节点本身的子网络的特定路由。

公开(公告)号：US06344404B1

公开(公告)日：2002-02-05

申请号：US09431007

申请日：1999-11-01

申请人： Nathan W. Cheung ,  Xiang Lu ,  Chenming Hu

发明人： Nathan W. Cheung ,  Xiang Lu ,  Chenming Hu

IPC分类号： H01L21265

CPC分类号： H01L21/2236 ,  H01L21/76251 ,  Y10S438/977

摘要： A technique for fabricating substrates such as a silicon-on-insulator substrate using a plasma immersion ion implantation (“PIII”) system 10. The technique includes a method, which has a step of providing a substrate 2100. Ions are implanted 2109 into a surface of the substrate to a first desired depth to provide a first distribution of the ions using a plasma immersion ion implantation system 10. The implanted ions define a first thickness of material 2101 above the implant. Global energy is then increased of the substrate to initiate a cleaving action, where the cleaving action is sufficient to completely free the thickness of material from a remaining portion of the substrate. By way of the PIII system, the ions are introduced into the substrate in an efficient and cost effective manner.

摘要翻译： 用于使用等离子体浸没离子注入（“PIII”）系统10制造诸如绝缘体上硅衬底之类的衬底的技术。该技术包括具有提供衬底2100的步骤的方法。离子被植入2109 衬底的表面到第一期望深度，以使用等离子体浸没离子注入系统10提供离子的第一分布。注入的离子限定了植入物上方的材料2101的第一厚度。 然后，全部能量增加基底以引发裂解作用，其中分裂作用足以使材料的厚度从基底的剩余部分完全释放。 通过PIII系统，以有效和成本有效的方式将离子引入衬底。