公开(公告)号：US07214973B2

公开(公告)日：2007-05-08

申请号：US11070229

申请日：2005-03-03

申请人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

发明人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

摘要： A bipolar type semiconductor device capable of attaining high current gain and high cut-off frequency and performing a satisfactory transistor operation also in a high current region while maintaining a high breakdown voltage performance, as well as a method of manufacturing the semiconductor device, are provided. In a collector comprising a first semiconductor layer and a second semiconductor layer narrower in band gap than the first semiconductor layer, an impurity is doped so as to have a peak of impurity concentration within the second collector layer and so that the value of the peak is higher than the impurity concentration at any position within the first collector layer. It is preferable to adjust the concentration of the doped impurity in such a manner that a collector-base depletion layer extends up to the first collector layer.

摘要翻译： 提供一种能够在保持高的击穿电压性能的同时在高电流区域中获得高电流增益和高截止频率并执行令人满意的晶体管操作的双极型半导体器件，以及制造半导体器件的方法 。 在包含比第一半导体层窄的带隙的第一半导体层和第二半导体层的集电体中，掺杂杂质以使第二集电极层内的杂质浓度的峰值为峰值， 高于第一收集层内任何位置的杂质浓度。 优选以使得集电极 - 基极耗尽层向上延伸到第一集电极层的方式调节掺杂杂质的浓度。

公开(公告)号：US07521734B2

公开(公告)日：2009-04-21

申请号：US10855378

申请日：2004-05-28

申请人： Eiji Oue ,  Katsuyoshi Washio ,  Hiromi Shimamoto ,  Katsuya Oda ,  Makoto Miura

发明人： Eiji Oue ,  Katsuyoshi Washio ,  Hiromi Shimamoto ,  Katsuya Oda ,  Makoto Miura

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66287 ,  H01L29/7322

摘要： A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.

摘要翻译： 提供双极晶体管，其中基极电阻和基极集电极电容都减小，并且能够以高截止频率工作。 半导体器件被构造成使得发射极和非本征基极通过绝缘体侧壁和绝缘体侧壁的底面彼此分离，并且发射极大致在同一平面上。 外部基极和集电极区域通过绝缘体彼此分离。

公开(公告)号：US20060043418A1

公开(公告)日：2006-03-02

申请号：US11070229

申请日：2005-03-03

申请人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

发明人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

IPC分类号： H01L31/109

CPC分类号： H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

摘要： A bipolar type semiconductor device capable of attaining high current gain and high cut-off frequency and performing a satisfactory transistor operation also in a high current region while maintaining a high breakdown voltage performance, as well as a method of manufacturing the semiconductor device, are provided. In a collector comprising a first semiconductor layer and a second semiconductor layer narrower in band gap than the first semiconductor layer, an impurity is doped so as to have a peak of impurity concentration within the second collector layer and so that the value of the peak is higher than the impurity concentration at any position within the first collector layer. It is preferable to adjust the concentration of the doped impurity in such a manner that a collector-base depletion layer extends up to the first collector layer.

摘要翻译： 提供一种能够在保持高的击穿电压性能的同时在高电流区域中获得高电流增益和高截止频率并执行令人满意的晶体管操作的双极型半导体器件，以及制造半导体器件的方法 。 在包含比第一半导体层窄的带隙的第一半导体层和第二半导体层的集电体中，掺杂杂质以使第二集电极层内的杂质浓度的峰值为峰值， 高于第一收集层内任何位置的杂质浓度。 优选以使得集电极 - 基极耗尽层向上延伸到第一集电极层的方式调节掺杂杂质的浓度。

公开(公告)号：US07842973B2

公开(公告)日：2010-11-30

申请号：US11485287

申请日：2006-07-13

申请人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

发明人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/7378 ,  Y10S438/936

摘要： A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier generated upon increase of the collector current and enabling satisfactory transistor operation at high current.

摘要翻译： 一种半导体器件及其制造方法，其能够在保持高耐受电压的同时避免在导带中产生阻挡层并能够在高电流下进行高速晶体管的操作，以及其制造方法，其中， 集电体由禁带宽度窄于半导体衬底的材料形成，禁带从发射极侧向集电极侧逐步且连续地增加的区域设置在基体的内部，禁带 在基极集电体界面的宽度被设计为大于基极中的最小禁带宽度，由此集电极侧的基底边缘处的禁带宽度可以更接近半导体的禁带宽度 衬底，同时充分保持发射极基极附近的杂质效应，从而能够降低高度 在集电极电流增加时产生能量势垒，并且能够在高电流下令人满意的晶体管工作。

公开(公告)号：US07071500B2

公开(公告)日：2006-07-04

申请号：US10866673

申请日：2004-06-15

申请人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

发明人： Makoto Miura ,  Katsuyoshi Washio ,  Hiromi Shimamoto

IPC分类号： H01L31/072

CPC分类号： H01L29/66287 ,  H01L29/0821 ,  H01L29/41708 ,  H01L29/732

摘要： A bipolar semiconductor device including a collector layer covered at a portion of an outer periphery thereof with an insulating film and having a shape extending in an upper direction and a horizontal direction, with a gap being formed between the collector layer and the insulating film, and further including a base layer and an emitter layer disposed over the collector layer, and a manufacturing method of the semiconductor device. Since the collector layer has a shape extending in a portion thereof in the upward direction and the horizontal direction, an external collector region can be deleted, and both the parasitic capacitance and the collector capacitance in the intrinsic portion attributable to the collector can be decreased and, accordingly, a bipolar transistor capable of high speed operation at a reduced consumption power can be constituted.

摘要翻译： 一种双极半导体器件，包括在其外周的一部分上覆盖有绝缘膜并且具有在上方向和水平方向上延伸的形状的集电极层，在集电层和绝缘膜之间形成间隙，以及 还包括设置在集电极层上的基极层和发射极层，以及半导体器件的制造方法。 由于集电体层的一部分在上下方向和水平方向上延伸，所以可以消除外部集电极区域，能够减少归因于集电体的本征部分的寄生电容和集电极电容， 因此，可以构成能够以降低的消耗功率进行高速运转的双极型晶体管。

公开(公告)号：US20050001238A1

公开(公告)日：2005-01-06

申请号：US10855378

申请日：2004-05-28

申请人： Eiji Oue ,  Katsuyoshi Washio ,  Hiromi Shimamoto ,  Katsuya Oda ,  Makoto Miura

发明人： Eiji Oue ,  Katsuyoshi Washio ,  Hiromi Shimamoto ,  Katsuya Oda ,  Makoto Miura

IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L31/0328

CPC分类号： H01L29/66287 ,  H01L29/7322

摘要： A bipolar transistor is provided in which both the base resistance and the base-collector capacitance are reduced and which is capable of operating at a high cutoff frequency. The semiconductor device is structured so that the emitter and extrinsic base are separated from each other by an insulator sidewall and the bottom faces of the insulator sidewall, and the emitter are approximately on the same plane. The extrinsic base electrode and the collector region are separated from each other by an insulator.

摘要翻译： 提供双极晶体管，其中基极电阻和基极集电极电容都减小，并且能够以高截止频率工作。 半导体器件被构造成使得发射极和非本征基极通过绝缘体侧壁和绝缘体侧壁的底面彼此分离，并且发射极大致在同一平面上。 外部基极和集电极区域通过绝缘体彼此分离。

公开(公告)号：US20060169987A1

公开(公告)日：2006-08-03

申请号：US11072279

申请日：2005-03-07

申请人： Makoto Miura ,  Katsuya Oda ,  Katsuyoshi Washio

发明人： Makoto Miura ,  Katsuya Oda ,  Katsuyoshi Washio

IPC分类号： H01L33/00 ,  H01S5/20

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02529 ,  H01L33/12

摘要： A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.

摘要翻译： 在硅（Si）衬底上形成了高于先有层的穿透位错密度较低的高质量碳化硅（SiC）层。 以这样的方式制造半导体器件，即在Si衬底上形成有部分地Si密度高于Si衬底的半导体缓冲层，其半导体缓冲层的缺陷密度高于Si衬底，其上部形成有成对的多对面 与半导体衬底的表面取向对称，此外在层的顶部依次形成SiC层。

公开(公告)号：US07368763B2

公开(公告)日：2008-05-06

申请号：US11072279

申请日：2005-03-07

申请人： Makoto Miura ,  Katsuya Oda ,  Katsuyoshi Washio

发明人： Makoto Miura ,  Katsuya Oda ,  Katsuyoshi Washio

IPC分类号： H01L31/00 ,  H01L29/788

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02529 ,  H01L33/12

摘要： A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.

摘要翻译： 在硅（Si）衬底上形成了高于先有层的穿透位错密度较低的高质量碳化硅（SiC）层。 以这样的方式制造半导体器件，即在Si衬底上形成有部分地Si密度高于Si衬底的半导体缓冲层，其半导体缓冲层的缺陷密度高于Si衬底，其上部形成有成对的多对面 与半导体衬底的表面取向对称，此外在层的顶部依次形成SiC层。

公开(公告)号：US07095043B2

公开(公告)日：2006-08-22

申请号：US10790190

申请日：2004-03-02

申请人： Katsuya Oda ,  Nobuyuki Sugii ,  Makoto Miura ,  Isao Suzumura ,  Katsuyoshi Washio

发明人： Katsuya Oda ,  Nobuyuki Sugii ,  Makoto Miura ,  Isao Suzumura ,  Katsuyoshi Washio

IPC分类号： H01L29/06 ,  H01L31/0328

CPC分类号： H01L29/66068 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/1608

摘要： An (SiGe)C layer having a stoichiometric ratio of about 1:1 is locally formed on an Si layer, a large forbidden band width semiconductor device is prepared inside the layered structure thereof and an Si semiconductor integrated circuit is formed in the regions not formed with the layered structure, whereby high frequency high power operation of the device is enabled by the large forbidden band width semiconductor device and high performance is attained by hybridization of the Si integrated circuit.

摘要翻译： 在Si层上局部地形成化学计量比为约1:1的An（SiGe）C层，在其层叠结构内制备大的禁带宽半导体器件，并且在未形成的区域中形成Si半导体集成电路 具有分层结构，由此通过大的禁带宽半导体器件能够实现器件的高频高功率操作，并且通过Si集成电路的杂交获得高性能。

公开(公告)号：US08294213B2

公开(公告)日：2012-10-23

申请号：US12838445

申请日：2010-07-17

申请人： Makoto Miura ,  Shinichi Saito ,  Youngkun Lee ,  Katsuya Oda

发明人： Makoto Miura ,  Shinichi Saito ,  Youngkun Lee ,  Katsuya Oda

IPC分类号： H01L21/00 ,  H01L21/331 ,  H01L27/12

CPC分类号： H01L31/03921 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L31/028 ,  H01L31/103 ,  H01L31/1808 ,  Y02E10/547

摘要： A semiconductor photodiode device includes a semiconductor substrate, a first buffer layer containing a material different from that of the semiconductor substrate in a portion thereof, a first semiconductor layer formed above the buffer layer and having a lattice constant different from that of the semiconductor substrate, a second buffer layer formed above the first semiconductor layer and containing an element identical with that of the first semiconductor layer in a portion thereof, and a second semiconductor layer formed above the buffer layer in which a portion of the first semiconductor layer is formed of a plurality of island shape portions each surrounded with an insulating film, and the second buffer layer allows adjacent islands of the first semiconductor layer to coalesce with each other and is in contact with the insulating film.

摘要翻译： 半导体光电二极管装置包括半导体衬底，第一缓冲层，其部分含有不同于半导体衬底的材料;第一半导体层，形成在缓冲层上方，具有不同于半导体衬底的晶格常数; 第二缓冲层，形成在第一半导体层的上方，并且在其一部分中含有与第一半导体层相同的元件;以及第二半导体层，形成在缓冲层的上方，第一半导体层的一部分由 多个岛状部分，各自被绝缘膜包围，第二缓冲层允许第一半导体层的相邻岛状物彼此聚结并与绝缘膜接触。