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8 条记录 (耗时 0.022 秒)

    Coin checking apparatus
    1.
    发明授权
    Coin checking apparatus 失效
    硬币检查装置

    公开(公告)号：US4733766A

    公开(公告)日：1988-03-29

    申请号：US805114

    申请日：1985-12-04

    申请人： Mark Roberts ,  Adrian Lewis

    发明人： Mark Roberts ,  Adrian Lewis

    IPC分类号： G07D5/08 ,  G07D5/00

    CPC分类号： G07F1/048 ,  G07D5/08

    摘要： The arrival of a coin in a coin checking apparatus is detected by arranging for the coin to hit a member (16). The vibration caused by the impact causes a piezoelectric element (36,36a) to give a transient output signal which is used to switch on electronic circuitry of the coin checking apparatus. The circuitry is normally switched off and thus over a period of time the average power consumption of the coin checking apparatus is low so that it can be satisfactorily run from a battery.

    摘要翻译： 通过布置硬币来撞击构件（16）来检测硬币到达硬币检查装置。 由冲击引起的振动使得压电元件（36,36a）产生用于打开硬币检查装置的电子电路的瞬态输出信号。 电路通常被关闭，因此在一段时间内硬币检查装置的平均功耗很低，从而可以令人满意地从电池运行。

    Multiple parallel digital data stream channel controller architecture
    3.
    发明授权
    Multiple parallel digital data stream channel controller architecture 失效
    多并行数字数据流通道控制器架构

    公开(公告)号：US5822553A

    公开(公告)日：1998-10-13

    申请号：US614729

    申请日：1996-03-13

    申请人： James K. Gifford ,  Sridhar Begur ,  Adrian Lewis ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

    发明人： James K. Gifford ,  Sridhar Begur ,  Adrian Lewis ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

    IPC分类号： G06F13/12 ,  G06F13/36 ,  G06F13/38 ,  H04J3/22 ,  G06F8/00

    CPC分类号： G06F13/122

    摘要： A multiple data stream channel controller providing demand driven transport of multiple data streams concurrently in real time through a peripheral data channel coupled between a general purpose processor system and a special purpose processor system. The controller comprises a first bus master interface coupleable to a general purpose processor system bus, a second bus master interface coupleable to a special purpose processor system bus, a segmentable buffer memory and a controller that directs the transfer of data segments between the first and second bus master interfaces via the segmentable buffer memory. The controller is responsive to a plurality of signals provided by the special purpose processor bus to request transfer of successive data segments from a respective plurality of data streams staged in the segmentable buffer memory. The controller moderates the transfer of successive data segments of the respective plurality of data streams via the first bus master interface to the segmentable buffer memory.

    摘要翻译： 多数据流信道控制器通过耦合在通用处理器系统和专用处理器系统之间的外围数据信道实时同时提供多个数据流的需求驱动传输。 控制器包括可耦合到通用处理器系统总线的第一总线主机接口，可耦合到专用处理器系统总线的第二总线主机接口，可分段缓冲存储器和控制器，其指导数据段在第一和第二 总线主机接口通过可分段缓冲存储器。 控制器响应于由专用处理器总线提供的多个信号，以请求从可分段缓冲存储器中分段的相应多个数据流传送连续的数据段。 控制器调节经由第一总线主接口将相应多个数据流的连续数据段传送到可分段缓冲存储器。

    Methods and systems for incremental crypto processing of fragmented packets
    5.
    发明申请
    Methods and systems for incremental crypto processing of fragmented packets 审中-公开
    分段数据包的增量密码处理方法和系统

    公开(公告)号：US20070255947A1

    公开(公告)日：2007-11-01

    申请号：US11351331

    申请日：2006-02-08

    申请人： Abhijit Choudhury ,  Himanshu Shukla ,  Adrian Lewis ,  Shekhar Ambe ,  Sodhanshu Jain ,  Mohanakumari T. ,  Mathew Kayalackakom

    发明人： Abhijit Choudhury ,  Himanshu Shukla ,  Adrian Lewis ,  Shekhar Ambe ,  Sodhanshu Jain ,  Mohanakumari T. ,  Mathew Kayalackakom

    IPC分类号： H04L9/00

    CPC分类号： H04L9/0643 ,  H04L9/0637 ,  H04L9/3242 ,  H04L63/12

    摘要： Methods and systems for providing confidentiality and/or integrity to fragmented packet transmissions, without reassembly of the fragments, across wired and wireless communications networks are disclosed. Encryption of a first fragmented packet can be performed by using an initial encryption state variable and keying material resulting in a first ciphertext fragment and a first encryption state variable. Then encryption of a second fragments packet can be performed by using the first encryption state variable and the keying material resulting in a second ciphertext fragment. Decryption of fragments can be performed in a similar manner as encryption. Computation of a message authentication code can be performed by computing a first hash state value for a first block size of bytes of a first packet fragment using an initial hash state value, and storing the first hash value and a first set of remainder bytes of the first packet fragment. The computation of the MAC continues by combining the first set of remainder bytes to a second packet fragment of the plurality of packet fragments resulting in a combined packet fragment. The MAC can then be identified using the second hash state value.

    摘要翻译： 公开了用于对分段分组传输提供机密性和/或完整性的方法和系统，而不需要在有线和无线通信网络上重新组合分段。 可以通过使用初始加密状态变量和密钥材料来执行加密第一分段分组，从而产生第一密文片段和第一加密状态变量。 然后可以通过使用第一加密状态变量和产生第二密文片段的密钥材料来执行第二分段分组的加密。 碎片的解密可以以与加密类似的方式执行。 可以通过使用初始散列状态值计算第一分组片段的第一块大小的字节的第一散列状态值并存储第一散列值和第一散列值的第一组剩余字节来执行消息认证码的计算 第一个包片段。 通过将第一组剩余字节组合到多个分组片段中的第二分组片段，导致MAC的计算，导致组合的分组片段。 然后可以使用第二散列状态值来识别MAC。

    Multiple parallel digital data stream channel controller
    6.
    发明授权
    Multiple parallel digital data stream channel controller 失效
    多并行数字数据流通道控制器

    公开(公告)号：US6044225A

    公开(公告)日：2000-03-28

    申请号：US596921

    申请日：1996-03-13

    申请人： Donald J. Spencer ,  James K. Gifford ,  Sridhar Begur ,  Adrian Lewis ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

    发明人： Donald J. Spencer ,  James K. Gifford ,  Sridhar Begur ,  Adrian Lewis ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

    IPC分类号： G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F13/00 ,  G06F13/42

    CPC分类号： G06F13/124 ,  G06F13/4059

    摘要： A data channel controller, coupleable to a base computer system including a base memory, for managing the transport of multiple data streams through a base system interface including a first buffer, a pool memory including a plurality of second buffers, and one or more peripheral devices each having a third buffer. An arbiter system is coupled to said pool memory for selectively enabling the transfer of data with respect to a predetermined first buffer in response to first and second request signals. The peripheral devices operate to transport data through their third buffers with respect to a peripheral interfaces characterized as each having a predetermined data transfer rate. The peripheral devices first request signals to the arbiter system under first predetermined conditions with respect to the presence of data in corresponding third buffers to obtain a transfer of data between corresponding second and third buffers. The base system interface provides the second request signal under second predetermined conditions with respect to the presence of data in the second buffers to obtain corresponding transfers of data between the second buffers and the base memory through the first buffer.

    摘要翻译： 一种数据通道控制器，可耦合到包括基本存储器的基本计算机系统，用于通过基本系统接口管理多个数据流的传输，所述基本系统接口包括第一缓冲器，包括多个第二缓冲器的池存储器以及一个或多个外围设备 每个具有第三缓冲器。 仲裁器系统耦合到所述池存储器，用于响应于第一和第二请求信号选择性地启用相对于预定第一缓冲器的数据传输。 外围设备操作以相对于以每个具有预定数据传输速率为特征的外围接口传输数据通过其第三缓冲器。 外围设备首先在第一预定条件下向相关的第三缓冲器中的数据存在请求仲裁系统的信号，以获得对应的第二和第三缓冲器之间的数据传输。 基本系统接口在第二预定条件下提供关于第二缓冲器中的数据存在的第二请求信号，以通过第一缓冲器获得第二缓冲器和基本存储器之间的数据的相应传输。

    System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs
    7.
    发明授权
    System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs 失效
    用于管理池存储器内的FIFO和外围设备之间的数据传输的系统，可通过FIFO的标识进行编程

    公开(公告)号：US5797043A

    公开(公告)日：1998-08-18

    申请号：US615682

    申请日：1996-03-13

    申请人： Adrian Lewis ,  James K. Gifford ,  Sridhar Begur ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

    发明人： Adrian Lewis ,  James K. Gifford ,  Sridhar Begur ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

    IPC分类号： G06F13/12 ,  G06F13/18 ,  G06F15/177 ,  G06F15/02

    CPC分类号： G06F13/18

    摘要： A data transfer control system including a pool memory, a plurality of peripheral devices, and a transfer controller. The pool memory provides for the storage of data in a plurality of FIFOs formed within the pool memory. The plurality of peripheral devices are coupleable to the pool memory to provide for the transfer of data between programmatically associated FIFOs and peripheral devices. The transfer controller is coupled to the pool memory and to the peripheral devices for selectively managing the transfer of data between the FIFOs and the peripheral devices. The transfer controller includes a distributed signaling system coupled to the peripheral devices to permit the broadcast of status information reflective of a transfer of data relative to a predetermined FIFO to the peripheral devices.

    摘要翻译： 一种包括池存储器，多个外围设备和传送控制器的数据传输控制系统。 池存储器提供在池存储器中形成的多个FIFO中的数据的存储。 多个外围设备可耦合到池存储器以提供在编程相关联的FIFO和外围设备之间传输数据。 转移控制器耦合到池存储器和外围设备，以选择性地管理FIFO和外围设备之间的数据传输。 转移控制器包括耦合到外围设备的分布式信令系统，以允许广播反映相对于外围设备的预定FIFO的数据传输的状态信息。

    Multi-threaded FIFO pool buffer and bus transfer control system
    8.
    发明授权
    Multi-threaded FIFO pool buffer and bus transfer control system 失效
    多线程FIFO池缓冲器和总线传输控制系统

    公开(公告)号：US5784649A

    公开(公告)日：1998-07-21

    申请号：US614659

    申请日：1996-03-13

    申请人： Sridhar Begur ,  James K. Gifford ,  Adrian Lewis ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

    发明人： Sridhar Begur ,  James K. Gifford ,  Adrian Lewis ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

    IPC分类号： G06F13/362 ,  G06F9/38 ,  G06F13/12 ,  G06F13/38 ,  G06F13/00

    CPC分类号： G06F9/3879 ,  G06F13/124

    摘要： A bus transfer control system manages the transfer of multiple asynchronous data streams through a buffer pool. The bus transfer control system includes a buffer pool having a plurality of memory blocks, wherein each memory block provides for the storage of a plurality of data bytes and a plurality of data transfer devices coupled to the buffer pool to allow the transfer of segments of one or more data streams to be transferred between the plurality of data tranfer devices through the buffer pool. A transfer controller maintains status information relating to the status of data in the memory blocks and includes control logic for repeatedly evaluating the status information and providing for the prioritied selection of a first data transfer device and a predetermined one of the memory blocks.

    摘要翻译： 总线传输控制系统通过缓冲池管理多个异步数据流的传输。 总线传输控制系统包括具有多个存储器块的缓冲池，其中每个存储器块提供多个数据字节的存储和耦合到缓冲池的多个数据传送设备，以允许传送一个 或更多数据流通过缓冲池在多个数据传送设备之间传送。 传送控制器维护与存储器块中的数据状态有关的状态信息，并且包括控制逻辑，用于重复地评估状态信息并提供第一数据传送装置和预定的一个存储块的优先选择。