公开(公告)号：US5822553A

公开(公告)日：1998-10-13

申请号：US614729

申请日：1996-03-13

申请人： James K. Gifford ,  Sridhar Begur ,  Adrian Lewis ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

发明人： James K. Gifford ,  Sridhar Begur ,  Adrian Lewis ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

IPC分类号： G06F13/12 ,  G06F13/36 ,  G06F13/38 ,  H04J3/22 ,  G06F8/00

CPC分类号： G06F13/122

摘要： A multiple data stream channel controller providing demand driven transport of multiple data streams concurrently in real time through a peripheral data channel coupled between a general purpose processor system and a special purpose processor system. The controller comprises a first bus master interface coupleable to a general purpose processor system bus, a second bus master interface coupleable to a special purpose processor system bus, a segmentable buffer memory and a controller that directs the transfer of data segments between the first and second bus master interfaces via the segmentable buffer memory. The controller is responsive to a plurality of signals provided by the special purpose processor bus to request transfer of successive data segments from a respective plurality of data streams staged in the segmentable buffer memory. The controller moderates the transfer of successive data segments of the respective plurality of data streams via the first bus master interface to the segmentable buffer memory.

摘要翻译： 多数据流信道控制器通过耦合在通用处理器系统和专用处理器系统之间的外围数据信道实时同时提供多个数据流的需求驱动传输。 控制器包括可耦合到通用处理器系统总线的第一总线主机接口，可耦合到专用处理器系统总线的第二总线主机接口，可分段缓冲存储器和控制器，其指导数据段在第一和第二 总线主机接口通过可分段缓冲存储器。 控制器响应于由专用处理器总线提供的多个信号，以请求从可分段缓冲存储器中分段的相应多个数据流传送连续的数据段。 控制器调节经由第一总线主接口将相应多个数据流的连续数据段传送到可分段缓冲存储器。

公开(公告)号：US6044225A

公开(公告)日：2000-03-28

申请号：US596921

申请日：1996-03-13

申请人： Donald J. Spencer ,  James K. Gifford ,  Sridhar Begur ,  Adrian Lewis ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

发明人： Donald J. Spencer ,  James K. Gifford ,  Sridhar Begur ,  Adrian Lewis ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

IPC分类号： G06F13/12 ,  G06F13/38 ,  G06F13/40 ,  G06F13/00 ,  G06F13/42

CPC分类号： G06F13/124 ,  G06F13/4059

摘要： A data channel controller, coupleable to a base computer system including a base memory, for managing the transport of multiple data streams through a base system interface including a first buffer, a pool memory including a plurality of second buffers, and one or more peripheral devices each having a third buffer. An arbiter system is coupled to said pool memory for selectively enabling the transfer of data with respect to a predetermined first buffer in response to first and second request signals. The peripheral devices operate to transport data through their third buffers with respect to a peripheral interfaces characterized as each having a predetermined data transfer rate. The peripheral devices first request signals to the arbiter system under first predetermined conditions with respect to the presence of data in corresponding third buffers to obtain a transfer of data between corresponding second and third buffers. The base system interface provides the second request signal under second predetermined conditions with respect to the presence of data in the second buffers to obtain corresponding transfers of data between the second buffers and the base memory through the first buffer.

摘要翻译： 一种数据通道控制器，可耦合到包括基本存储器的基本计算机系统，用于通过基本系统接口管理多个数据流的传输，所述基本系统接口包括第一缓冲器，包括多个第二缓冲器的池存储器以及一个或多个外围设备 每个具有第三缓冲器。 仲裁器系统耦合到所述池存储器，用于响应于第一和第二请求信号选择性地启用相对于预定第一缓冲器的数据传输。 外围设备操作以相对于以每个具有预定数据传输速率为特征的外围接口传输数据通过其第三缓冲器。 外围设备首先在第一预定条件下向相关的第三缓冲器中的数据存在请求仲裁系统的信号，以获得对应的第二和第三缓冲器之间的数据传输。 基本系统接口在第二预定条件下提供关于第二缓冲器中的数据存在的第二请求信号，以通过第一缓冲器获得第二缓冲器和基本存储器之间的数据的相应传输。

公开(公告)号：US5797043A

公开(公告)日：1998-08-18

申请号：US615682

申请日：1996-03-13

申请人： Adrian Lewis ,  James K. Gifford ,  Sridhar Begur ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

发明人： Adrian Lewis ,  James K. Gifford ,  Sridhar Begur ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

IPC分类号： G06F13/12 ,  G06F13/18 ,  G06F15/177 ,  G06F15/02

CPC分类号： G06F13/18

摘要： A data transfer control system including a pool memory, a plurality of peripheral devices, and a transfer controller. The pool memory provides for the storage of data in a plurality of FIFOs formed within the pool memory. The plurality of peripheral devices are coupleable to the pool memory to provide for the transfer of data between programmatically associated FIFOs and peripheral devices. The transfer controller is coupled to the pool memory and to the peripheral devices for selectively managing the transfer of data between the FIFOs and the peripheral devices. The transfer controller includes a distributed signaling system coupled to the peripheral devices to permit the broadcast of status information reflective of a transfer of data relative to a predetermined FIFO to the peripheral devices.

摘要翻译： 一种包括池存储器，多个外围设备和传送控制器的数据传输控制系统。 池存储器提供在池存储器中形成的多个FIFO中的数据的存储。 多个外围设备可耦合到池存储器以提供在编程相关联的FIFO和外围设备之间传输数据。 转移控制器耦合到池存储器和外围设备，以选择性地管理FIFO和外围设备之间的数据传输。 转移控制器包括耦合到外围设备的分布式信令系统，以允许广播反映相对于外围设备的预定FIFO的数据传输的状态信息。

公开(公告)号：US5784649A

公开(公告)日：1998-07-21

申请号：US614659

申请日：1996-03-13

申请人： Sridhar Begur ,  James K. Gifford ,  Adrian Lewis ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

发明人： Sridhar Begur ,  James K. Gifford ,  Adrian Lewis ,  Donald J. Spencer ,  Thomas E. Kilbourn ,  Daniel B. Gochnauer

IPC分类号： G06F13/362 ,  G06F9/38 ,  G06F13/12 ,  G06F13/38 ,  G06F13/00

CPC分类号： G06F9/3879 ,  G06F13/124

摘要： A bus transfer control system manages the transfer of multiple asynchronous data streams through a buffer pool. The bus transfer control system includes a buffer pool having a plurality of memory blocks, wherein each memory block provides for the storage of a plurality of data bytes and a plurality of data transfer devices coupled to the buffer pool to allow the transfer of segments of one or more data streams to be transferred between the plurality of data tranfer devices through the buffer pool. A transfer controller maintains status information relating to the status of data in the memory blocks and includes control logic for repeatedly evaluating the status information and providing for the prioritied selection of a first data transfer device and a predetermined one of the memory blocks.

摘要翻译： 总线传输控制系统通过缓冲池管理多个异步数据流的传输。 总线传输控制系统包括具有多个存储器块的缓冲池，其中每个存储器块提供多个数据字节的存储和耦合到缓冲池的多个数据传送设备，以允许传送一个 或更多数据流通过缓冲池在多个数据传送设备之间传送。 传送控制器维护与存储器块中的数据状态有关的状态信息，并且包括控制逻辑，用于重复地评估状态信息并提供第一数据传送装置和预定的一个存储块的优先选择。

公开(公告)号：US06940807B1

公开(公告)日：2005-09-06

申请号：US09699193

申请日：2000-10-26

申请人： Behrooz Rezvani ,  Avadhani Shridhar ,  Raminder S. Bajwa ,  Tiruvur R. Ramesh ,  Masoud Eskandari ,  Firooz Massoudi ,  Sam Heidari ,  Omprakash S. Sarmaru ,  Sridhar Begur

发明人： Behrooz Rezvani ,  Avadhani Shridhar ,  Raminder S. Bajwa ,  Tiruvur R. Ramesh ,  Masoud Eskandari ,  Firooz Massoudi ,  Sam Heidari ,  Omprakash S. Sarmaru ,  Sridhar Begur

IPC分类号： H04J11/00

CPC分类号： G06F17/142 ,  H04L27/2628 ,  H04L27/265

摘要： The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) portions across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session. The DSP offers the speed associated with hardware implementation of the transforms and the flexibility of a software only implementation. Traffic flow is regulated in the chip using a packet based schema in which each packet is associated with a specific channel of upstream and downstream data. Header and control information in each packet is used to govern the processing of each packet as it moves along either the transmit path or receive path. The DSP of the current invention may advantageously be utilized in fields other than communications, such as: medical and other imaging, seismic analysis, radar and other military applications, pattern recognition, signal processing etc. The present invention provides a signal processing architecture that supports scalability of CO/DLC/ONU resources, and allows a significantly more flexible hardware response to the evolving X-DSL standards without over committing of hardware resources. As standards evolve hardware may be reconfigured to support the new standards.

摘要翻译： 本发明提供一种DSP，其容纳多个当前的X-DSL协议，并且可进一步配置以支持未来的协议。 DSP在传输和接收路径上都具有共享和专用硬件组件。 DSP在宽范围的采样大小和X-DSL协议上实现离散傅立叶变换（DFT）和离散傅立叶逆变换（IDFT）部分。 每个具有不同的X-DSL协议的多个信道可以在同一个会话中处理。 DSP提供与转换的硬件实现相关的速度和仅用于软件的实现的灵活性。 使用基于分组的模式在芯片中调整流量流，其中每个分组与上游和下游数据的特定信道相关联。 每个数据包中的报头和控制信息用于控制每个数据包沿着发送路径或接收路径移动时的处理。 本发明的DSP可有利地用于通信以外的领域，例如：医疗和其他成像，地震分析，雷达和其他军事应用，模式识别，信号处理等。本发明提供一种信号处理架构，其支持 CO / DLC / ONU资源的可扩展性，并且允许对演进的X-DSL标准的显着更灵活的硬件响应，而不必超过硬件资源。 随着标准的发展，硬件可能被重新配置以支持新的标准。

公开(公告)号：US07028063B1

公开(公告)日：2006-04-11

申请号：US09698824

申请日：2000-10-26

申请人： Omprakash S. Sarmaru ,  Raminder S. Bajwa ,  Sridhar Begur ,  Avadhani Shridhar ,  Sam Heid Ari ,  Behrooz Rezvani

发明人： Omprakash S. Sarmaru ,  Raminder S. Bajwa ,  Sridhar Begur ,  Avadhani Shridhar ,  Sam Heid Ari ,  Behrooz Rezvani

IPC分类号： F06F17/14

CPC分类号： G06F17/141 ,  H04L27/2628 ,  H04L27/265

摘要： A Fourier transform processor utilizing discrete circuits each of which is configurable for processing a wide range of sample sizes. A single pipeline supports multiplexed bi-directional transformations between for example the time and frequency domains. In an embodiment of the invention the Fourier Transform processor may be implemented as part of a digital signal processor (DSP). In this embodiment the DSP may implement both the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) across a wide range of sample sizes and X-DSL protocols. Multiple channels, each with varying ones of the X-DSL protocols can be handled in the same session.

摘要翻译： 利用离散电路的傅里叶变换处理器，每个离散电路可配置用于处理各种样本大小的范围。 单个流水线支持例如时域和频域之间的复用双向变换。 在本发明的实施例中，傅里叶变换处理器可以被实现为数字信号处理器（DSP）的一部分。 在该实施例中，DSP可以在宽范围的样本大小和X-DSL协议上实现离散傅里叶变换（DFT）和离散傅里叶逆变换（IDFT）两者。 每个具有不同的X-DSL协议的多个信道可以在同一个会话中处理。

公开(公告)号：US06202120B1

公开(公告)日：2001-03-13

申请号：US09364480

申请日：1999-07-30

申请人： Marilyn Jean Lang ,  Sridhar Begur ,  Robert Campbell ,  Carol Elise Bassett

发明人： Marilyn Jean Lang ,  Sridhar Begur ,  Robert Campbell ,  Carol Elise Bassett

IPC分类号： G06F1202

CPC分类号： G06F13/4243 ,  G06F12/0879

摘要： A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

摘要翻译： 微机系统存储器架构和方法允许系统存储器以突发模式以高速提供数据访问。 该架构和方法利用能够执行系统存储器寻址的系统存储器控制器。 微处理器和系统存储器通过高速主机总线进行通信。 系统存储器由多个64位系统存储器总线组成，以允许高速数据以突发模式传输到微处理器，而不需要外部高速缓存。

公开(公告)号：US5732406A

公开(公告)日：1998-03-24

申请号：US950979

申请日：1992-09-23

申请人： Carol Elise Bassett ,  Robert Gregory Campbell ,  Marilyn Jean Lang ,  Sridhar Begur

发明人： Carol Elise Bassett ,  Robert Gregory Campbell ,  Marilyn Jean Lang ,  Sridhar Begur

IPC分类号： G06F12/02 ,  G06F12/08 ,  G06F13/16 ,  G06F13/28 ,  G06F13/14

CPC分类号： G06F13/28 ,  G06F12/0879 ,  G06F13/1631

摘要： A microcomputer architecture and method allows for high processing speeds. A microprocessor constitutes the central processing unit. The microprocessor comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit and the system memory communicate by way of a high speed host bus. The system memory is comprised of multiple buses and is capable of delivering data to the microprocessor in a burst mode at high speeds. A memory controller addresses data locations within the system memory upon receipt of a first host address from the microprocessor. Accordingly, the microprocessor can access data in the system memory at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.

摘要翻译： 微机架构和方法允许高处理速度。 微处理器构成中央处理单元。 微处理器包括片上缓存存储器，并且能够以突发模式读取数据。 中央处理单元和系统存储器通过高速主机总线进行通信。 系统存储器由多条总线组成，能够以突发模式高速传送数据给微处理器。 存储器控制器在从微处理器接收到第一主机地址时寻址系统存储器内的数据位置。 因此，当以突发模式操作时，微处理器可以以非常快的速率访问系统存储器中的数据。 高速处理完成，无需外部缓存。

公开(公告)号：US5301328A

公开(公告)日：1994-04-05

申请号：US951650

申请日：1992-09-25

申请人： Sridhar Begur ,  Irvin R. Jones, Jr.

发明人： Sridhar Begur ,  Irvin R. Jones, Jr.

IPC分类号： G06F12/06 ,  G06F12/02

CPC分类号： G06F12/0638

摘要： A system and method for managing the reserved memory in a microcomputer copies selected portions of reserved memory to a new reserved memory having a faster access time, and allows any free portions of the new reserved memory to be accessed by a typical software application. After the selected portions of reserved memory are copied, all access to an address within a selected portion are re-directed to the new reserved memory. Any free portions of new reserved memory have additional, accessible memory re-mapped to these free portions.

摘要翻译： 用于管理微型计算机的保留存储器的系统和方法将预留存储器的选定部分复制到具有更快访问时间的新的预留存储器，并且允许新的预留存储器的任何空闲部分由典型的软件应用程序访问。 在保留存储器的所选部分被复制之后，对所选部分内的地址的所有访问被重新定向到新的预留存储器。 新的预留内存的任何空闲部分都有额外的可访问内存重新映射到这些空闲部分。

公开(公告)号：US5202994A

公开(公告)日：1993-04-13

申请号：US472057

申请日：1990-01-31

申请人： Sridhar Begur ,  Irvin R. Jones, Jr.

发明人： Sridhar Begur ,  Irvin R. Jones, Jr.

IPC分类号： G06F12/06

CPC分类号： G06F12/0638

摘要： A system and method for managing the reserved memory in a microcomputer copies selected portions of reserved memory to a new reserved memory having a faster access time, and allows any free portions of the new reserved memory to be accessed by a typical software application. After the selected portions of reserved memory are copied, all access to an address within a selected portion are re-directed to the new reserved memory. Any free portions of new reserved memory have additional, accessible memory re-mapped to these free portions.