公开(公告)号：US20070148973A1

公开(公告)日：2007-06-28

申请号：US11319895

申请日：2005-12-28

申请人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

发明人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

IPC分类号： H01L21/302 ,  B44C1/22 ,  H01L21/461

CPC分类号： H01L21/28123 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

摘要翻译： 使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。 在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。 第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。 第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。 最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以产生 类似的最终结构。

公开(公告)号：US07365018B2

公开(公告)日：2008-04-29

申请号：US11319895

申请日：2005-12-28

申请人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

发明人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

IPC分类号： H01L21/302

CPC分类号： H01L21/28123 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

摘要翻译： 使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。 在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。 第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。 第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。 最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以形成 类似的最终结构。

公开(公告)号：US07436019B2

公开(公告)日：2008-10-14

申请号：US11622634

申请日：2007-01-12

申请人： Jeffrey W. Lutze ,  Tuan Pham ,  Masaaki Higashitani

发明人： Jeffrey W. Lutze ,  Tuan Pham ,  Masaaki Higashitani

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521

摘要： A non-volatile memory array has word lines coupled to floating gates, the floating gates having an upper portion that is adapted to provide increased surface area, and thereby, to provide increased coupling to the word lines. Shielding between floating gates is also provided. The upper portion covers part of a lower portion of the floating gate and leaves a part of the lower portion uncovered. A control gate is coplanar with a top surface of the upper portion, a vertical side of the upper portion, and the uncovered portion of the lower portion.

摘要翻译： 非易失性存储器阵列具有耦合到浮动栅极的字线，浮动栅极具有适于提供增加的表面积的上部部分，从而提供增加的与字线的耦合。 还提供了浮动门之间的屏蔽。 上部覆盖浮动门的下部的一部分并且使下部的未被覆盖的部分离开。 控制栅极与上部的上表面，上部的垂直侧和下部的未覆盖部分共面。

公开(公告)号：US20080248621A1

公开(公告)日：2008-10-09

申请号：US12058512

申请日：2008-03-28

申请人： James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  George Matamis ,  Takashi Orimoto

发明人： James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  George Matamis ,  Takashi Orimoto

IPC分类号： H01L21/336

CPC分类号： H01L27/11529 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.

摘要翻译： 提供非易失性存储器和集成存储器和外围电路制造工艺。 使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。 中间电介质层设置在电荷存储区域的上方。 将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。 从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。 外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。 这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

公开(公告)号：US20080074920A1

公开(公告)日：2008-03-27

申请号：US11534139

申请日：2006-09-21

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： G11C5/06

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。 具有倒T形浮置栅极的阵列可以以自对准的方式形成。

公开(公告)号：US20070087504A1

公开(公告)日：2007-04-19

申请号：US11254142

申请日：2005-10-18

申请人： Tuan Pham ,  Masaaki Higashitani

发明人： Tuan Pham ,  Masaaki Higashitani

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L27/11526 ,  H01L21/31111 ,  H01L21/3212 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11531

摘要： A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with the underlying dielectric. A conductive layer overlies the substrate during implantation. A substrate having small polysilicon features in a memory array and large polysilicon features in a peripheral area is accurately planarized using protrusions in the peripheral area and a soft chemical mechanical polishing step that stops when protrusions are removed.

摘要翻译： 形成在浮动栅极之间具有浅沟槽隔离结构并且具有在浮动栅极之间延伸的控制栅极的非易失性存储器，其中浅沟槽隔离电介质被蚀刻。 使用离子注入实现蚀刻深度的控制，以与下层电介质相比形成具有高蚀刻速率的电介质层。 在植入期间，导电层覆盖衬底。 存储器阵列中具有小的多晶硅特征的基板和外围区域中的大多晶硅特征使用周边区域中的突起精细地平坦化，并且当突起被去除时停止的软化学机械抛光步骤。

公开(公告)号：US20120243337A1

公开(公告)日：2012-09-27

申请号：US13153964

申请日：2011-06-06

申请人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

发明人： Sanghyun Lee ,  Mohan Dunga ,  Masaaki Higashitani ,  Tuan Pham ,  Franz Kreupl

IPC分类号： G11C16/10 ,  G11C16/04 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42324

摘要： Non-volatile storage elements having a P−/metal floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have a metal region near the control gate. A P− region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

摘要翻译： 本文公开了具有P- /金属浮动栅极的非易失性存储元件。 浮栅可以在隧道氧化物附近具有P-区域，并且可以在控制栅极附近具有金属区域。 隧道氧化物附近的P-区域有助于提供良好的数据保留。 控制栅极附近的金属区域有助于实现控制栅极和浮动栅极之间良好的耦合比。 因此，非易失性存储元件的编程是有效的。 此外，擦除非易失性存储元件可能是有效的。 在一些实施例中，在隧道氧化物附近具有P-区（与强掺杂p型半导体相反）可提高相对于P +的擦除效率。

公开(公告)号：US07615445B2

公开(公告)日：2009-11-10

申请号：US11534135

申请日：2006-09-21

申请人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

发明人： Henry Chien ,  George Matamis ,  Tuan Pham ,  Masaaki Higashitani ,  Hidetaka Horiuchi ,  Jeffrey W. Lutze ,  Nima Mokhlesi ,  Yupin Kawing Fong

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. An array having inverted-T shaped floating gates may be formed in a self-aligned manner.

摘要翻译： 非易失性存储器阵列包括沿着垂直于浮动单元连接在一起以形成串的方向的平面的横截面具有倒T形的浮动栅极。 相邻的串由浅沟槽隔离结构隔离。 具有倒T形浮置栅极的阵列可以以自对准的方式形成。

公开(公告)号：US07582529B2

公开(公告)日：2009-09-01

申请号：US12061641

申请日：2008-04-02

申请人： George Matamis ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  Tuan Pham

发明人： George Matamis ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  Tuan Pham

IPC分类号： H01L21/8247

CPC分类号： H01L27/11543 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541

摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor. Control gate interconnects can be formed to connect together rows of isolated control gates to extrinsically form word lines.

摘要翻译： 提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成的外围电路形成形成其的方法。 形成沿着行方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。 形成条带限定了所得电荷存储结构在列方向上的尺寸。 在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。 控制栅极材料条形成在沿着列方向相邻的电荷存储材料的条带之间。 电荷存储和控制栅极材料条沿着它们在行方向上的长度被划分，作为形成隔离沟槽和有源区的列的一部分。 在分割条之后，蚀刻衬底的外围电路区域处的电荷存储材料，以便在外围晶体管的列方向上限定栅极尺寸。 可以形成控制栅极互连以将行隔离的控制栅极连接在一起，以外部地形成字线。

公开(公告)号：US20080171406A1

公开(公告)日：2008-07-17

申请号：US12014689

申请日：2008-01-15

申请人： Takashi Orimoto ,  George Matamis ,  James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  Henry Chien

发明人： Takashi Orimoto ,  George Matamis ,  James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  Henry Chien

IPC分类号： H01L21/8247

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

摘要： Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.

摘要翻译： 使用复合间隔物形成工艺提供制造集成电路器件的方法。 当形成设备的选择特征时，使用复合间隔物结构来图案化和蚀刻层堆叠。 复合存储结构包括由第一隔离物材料层形成的第一间隔物和由第二隔离物材料层形成的第二和第三间隔物。 该方法适用于制造具有小于所使用的光刻工艺的最小可分辨特征尺寸的线和空间尺寸的装置。 此外，等于线和空间大小小于最小特征尺寸。 在一个实施例中，使用复合间隔结构形成双控制非易失性闪存存储元件阵列。 当形成衬底的活性区域时，具有叠层的叠层和隔离区之间的复合间隔结构有利于条之间的等长长度和隔离区。