公开(公告)号：US07542859B2

公开(公告)日：2009-06-02

申请号：US11394859

申请日：2006-03-31

Applicant: Merritt Funk ,  Daniel J. Prager

Inventor： Merritt Funk ,  Daniel J. Prager

IPC: G01R13/00

CPC classification number: G01B11/24 ,  G01N21/211 ,  G01N21/4788 ,  G01N21/95607 ,  G01N2021/213 ,  G01N2021/95615

Abstract: A method of creating a virtual profile library includes obtaining a reference signal. The reference signal is compared to a plurality of signals in a first library. The reference signal is compared to a plurality of signals in a second library. A virtual profile data space is created when first and second matching criteria are not met. The virtual profile data space is created using differences between a profile data spaces associated with the first and second libraries. A first virtual profile signal is created in the virtual profile data space. A difference is calculated between the reference signal and the first virtual profile signal. The difference is compared to a virtual profile library creation criteria. If the virtual profile library creation criteria is met, the first virtual profile signal and the virtual profile data, associated with the first virtual profile signal is stored.

Abstract translation: 创建虚拟简档库的方法包括获得参考信号。 将参考信号与第一库中的多个信号进行比较。 将参考信号与第二库中的多个信号进行比较。 当不满足第一和第二匹配条件时，创建虚拟配置文件数据空间。 使用与第一和第二库相关联的简档数据空间之间的差异来创建虚拟简档数据空间。 在虚拟配置文件数据空间中创建第一虚拟配置文件信号。 在参考信号和第一虚拟轮廓信号之间计算差。 将差异与虚拟简档库创建标准进行比较。 如果满足虚拟简档库创建标准，则存储与第一虚拟简档信号相关联的第一虚拟简档信号和虚拟简档数据。

公开(公告)号：US07487053B2

公开(公告)日：2009-02-03

申请号：US11394860

申请日：2006-03-31

Applicant: Merritt Funk ,  Daniel J. Prager

Inventor： Merritt Funk ,  Daniel J. Prager

IPC: G01F19/00

CPC classification number: G01N21/4788

Abstract: A method of refining a virtual profile library includes obtaining a reference signal measured off a reference structure on a semiconductor wafer with a metrology device. A best match is selected of the reference signal in a virtual profile data space. The virtual profile data space has data points with specified accuracy values. The data points represent virtual profile parameters and associated virtual profile signals. The virtual profile parameters characterize the profile of an integrated circuit structure. The best match being a data point of the profile data space with a signal closest to the reference signal. Refined virtual profile parameters are determined corresponding to the reference signal based on the virtual profile parameters of the selected virtual profile signal using a refinement procedure.

Abstract translation: 精细虚拟简档库的方法包括：使用测量装置获得在半导体晶片上的参考结构测量的参考信号。 在虚拟简档数据空间中选择参考信号的最佳匹配。 虚拟配置文件数据空间具有指定精度值的数据点。 数据点表示虚拟轮廓参数和相关联的虚拟轮廓信号。 虚拟轮廓参数表征集成电路结构的轮廓。 最佳匹配是具有最接近参考信号的信号的简档数据空间的数据点。 使用细化过程，基于所选虚拟简档信号的虚拟简档参数，对应于参考信号来确定精细虚拟简档参数。

公开(公告)号：US08532796B2

公开(公告)日：2013-09-10

申请号：US13077705

申请日：2011-03-31

Applicant: Daniel J Prager ,  Merritt Funk ,  Peter Biolsi ,  Ryukichi Shimizu

Inventor： Daniel J Prager ,  Merritt Funk ,  Peter Biolsi ,  Ryukichi Shimizu

IPC: H01L21/66 ,  G06F19/00

CPC classification number: H01L22/20 ,  H01J37/32082 ,  H01J37/3266 ,  H01L21/31116 ,  H01L21/823871 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

Abstract translation: 本发明提供了一种用于在图案化晶片上实时使用双模式接触蚀刻（DPCE）处理序列和相关联的接触蚀刻多输入/多输出（CE- MIMO）模型。 DPCE处理序列可以包括一个或多个接触蚀刻程序，一个或多个测量程序，一个或多个接触蚀刻建模程序以及一个或多个接触蚀刻验证程序。 CE-MIMO模型使用多层和/或多个接触蚀刻程序之间的动态交互行为建模。 多层和/或多层接触蚀刻程序可以与在双重图案化（DP）程序期间可以创建的线，沟槽，通孔，间隔物，接触和门结构的创建相关联。

公开(公告)号：US07939450B2

公开(公告)日：2011-05-10

申请号：US11859507

申请日：2007-09-21

Applicant: Asao Yamashita ,  Merritt Funk ,  Daniel J. Prager ,  Lee Chen ,  Radha Sundararajan

Inventor： Asao Yamashita ,  Merritt Funk ,  Daniel J. Prager ,  Lee Chen ,  Radha Sundararajan

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/32422 ,  H01L22/12 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.

Abstract translation: 本发明可以提供使用S-O处理序列处理衬底的方法以及可以包括一个或多个优化的间隔物产生和评估程序的评估库。

公开(公告)号：US20120253497A1

公开(公告)日：2012-10-04

申请号：US13077705

申请日：2011-03-31

Applicant: Daniel J. Prager ,  Merritt Funk ,  Peter Biolsi ,  Ryukichi Shimizu

Inventor： Daniel J. Prager ,  Merritt Funk ,  Peter Biolsi ,  Ryukichi Shimizu

IPC: H01L21/66 ,  G06F19/00

CPC classification number: H01L22/20 ,  H01J37/32082 ,  H01J37/3266 ,  H01L21/31116 ,  H01L21/823871 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a systems and methods for creating Double Pattern (DP) structures on a patterned wafer in real-time using Dual Pattern Contact-Etch (DPCE) processing sequences and associated Contact-Etch-Multi-Input/Multi-Output (CE-MIMO) models. The DPCE processing sequences can include one or more contact-etch procedures, one or more measurement procedures, one or more contact-etch modeling procedures, and one or more contact-etch verification procedures. The CE-MIMO model uses dynamically interacting behavioral modeling between multiple layers and/or multiple contact-etch procedures. The multiple layers and/or the multiple contact-etch procedures can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created during Double Patterning (DP) procedures.

Abstract translation: 本发明提供了一种用于在图案化晶片上实时使用双模式接触蚀刻（DPCE）处理序列和相关联的接触蚀刻多输入/多输出（CE- MIMO）模型。 DPCE处理序列可以包括一个或多个接触蚀刻程序，一个或多个测量程序，一个或多个接触蚀刻建模程序以及一个或多个接触蚀刻验证程序。 CE-MIMO模型使用多层和/或多个接触蚀刻程序之间的动态交互行为建模。 多层和/或多层接触蚀刻程序可以与在双重图案化（DP）程序期间可以创建的线，沟槽，通孔，间隔物，接触和门结构的创建相关联。

公开(公告)号：US20100214545A1

公开(公告)日：2010-08-26

申请号：US12391410

申请日：2009-02-24

Applicant: Merritt Funk ,  Daniel J. Prager ,  Asao Yamashita ,  Radha Sundararajan

Inventor： Merritt Funk ,  Daniel J. Prager ,  Asao Yamashita ,  Radha Sundararajan

IPC: G03B27/42 ,  G03C5/00

CPC classification number: G03B27/42 ,  G03F7/70466

Abstract: The invention can provide apparatus and methods of creating metal gate structures on wafers in real-time using Lithography-Etch-Lithography-Etch (LELE) processing sequence. Real-time data and/or historical data associated with LELE processing sequences can be fed forward and/or fed back as fixed variables or constrained variables in internal-Integrated-Metrology modules (i-IMM) to improve the accuracy of the metal gate structures.

Abstract translation: 本发明可以提供使用光刻蚀刻光刻蚀刻（LELE）处理序列实时地在晶片上形成金属栅极结构的设备和方法。 与LELE处理序列相关联的实时数据和/或历史数据可以作为内部集成计量模块（i-IMM）中的固定变量或约束变量进​​行向前馈送和/或反馈，以提高金属门结构的精度 。

公开(公告)号：US20090081815A1

公开(公告)日：2009-03-26

申请号：US11859507

申请日：2007-09-21

Applicant: Asao Yamashita ,  Merritt Funk ,  Daniel J. Prager ,  Lee Chen ,  Radha Sundararajan

Inventor： Asao Yamashita ,  Merritt Funk ,  Daniel J. Prager ,  Lee Chen ,  Radha Sundararajan

IPC: H01L21/311

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/32422 ,  H01L22/12 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.

Abstract translation: 本发明可以提供使用S-O处理序列处理衬底的方法以及可以包括一个或多个优化的间隔物产生和评估程序的评估库。

公开(公告)号：US07765077B2

公开(公告)日：2010-07-27

申请号：US11859596

申请日：2007-09-21

Applicant: Asao Yamashita ,  Merritt Funk ,  Daniel J. Prager ,  Lee Chen ,  Radha Sundaranajan

Inventor： Asao Yamashita ,  Merritt Funk ,  Daniel J. Prager ,  Lee Chen ,  Radha Sundaranajan

IPC: G01D18/00

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention can provide a method of processing a substrate using Spacer-Optimization (S-O) processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures. In addition, the S-O processing sequences can include one or more deposition procedures, one or more partial-etch procedures, one or more chemical oxide removal (COR)-etch procedures, one or more optimization procedures, one or more evaluation procedures, and/or one or more verification procedures.

Abstract translation: 本发明可以提供使用间隔优化（S-O）处理序列和评估库来处理底物的方法，其可以包括一个或多个优化的间隔物产生和评估程序。 此外，SO处理序列可以包括一个或多个沉积程序，一个或多个部分蚀刻程序，一个或多个化学氧化物去除（COR）获取程序，一个或多个优化程序，一个或多个评估程序和/ 或一个或多个验证程序。

公开(公告)号：US20090082983A1

公开(公告)日：2009-03-26

申请号：US11859596

申请日：2007-09-21

Applicant: Asao Yamashita ,  Merritt Funk ,  Daniel J. Prager ,  Lee Chen ,  Radha Sundararajan

Inventor： Asao Yamashita ,  Merritt Funk ,  Daniel J. Prager ,  Lee Chen ,  Radha Sundararajan

IPC: G06F19/00

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention can provide a method of processing a substrate using S-O processing sequences and evaluation libraries that can include one or more optimized spacer creation and evaluation procedures.

Abstract translation: 本发明可以提供使用S-O处理序列处理衬底的方法以及可以包括一个或多个优化的间隔物产生和评估程序的评估库。

公开(公告)号：US08847159B2

公开(公告)日：2014-09-30

申请号：US13433071

申请日：2012-03-28

Applicant: Lee Chen ,  Barton Lane ,  Merritt Funk ,  Jianping Zhao ,  Radha Sundararajan

Inventor： Lee Chen ,  Barton Lane ,  Merritt Funk ,  Jianping Zhao ,  Radha Sundararajan

IPC: G01T1/185 ,  H01J49/48 ,  H01J37/32 ,  H05H1/00

CPC classification number: H01J37/32935 ,  H01J49/488 ,  H05H1/0081 ,  Y10T29/49002

Abstract: An ion energy analyzer for determining an ion energy distribution of a plasma and comprising an entrance grid, a selection grid, and an ion collector. The entrance grid includes a first plurality of openings dimensioned to be less than a Debye length for the plasma. The ion collector is coupled to the entrance grid via a first voltage source. The selection grid is positioned between the entrance grid and the ion collector and is coupled to the entrance grid via a second voltage source. An ion current meter is coupled to the ion collector to measure an ion flux onto the ion collector and transmit a signal related thereto.

Abstract translation: 一种用于确定等离子体的离子能量分布并包括入口格栅，选择栅格和离子收集器的离子能量分析器。 入口格栅包括尺寸小于等离子体的德拜长度的第一多个开口。 离子收集器通过第一电压源耦合到入口电网。 选择网格位于入口格栅和离子收集器之间，并通过第二电压源耦合到入口格栅。 离子电流计耦合到离子收集器以测量离子收集器上的离子通量并传输与其相关的信号。