公开(公告)号：US11682642B2

公开(公告)日：2023-06-20

申请号：US17019768

申请日：2020-09-14

Applicant: Microchip Technology incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Andrew Taylor

IPC: H01L23/00 ,  H01L23/10 ,  H01L21/768

CPC classification number: H01L24/09 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/49 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05019 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/386 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

公开(公告)号：US10818748B2

公开(公告)日：2020-10-27

申请号：US16034394

申请日：2018-07-13

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Bonnie Hamlin ,  Andrew Taylor ,  Janet Vanderiet ,  Justin Sato

IPC: H01L49/02 ,  H01L21/285 ,  H01L21/311

Abstract: A method for manufacturing a thin film resistor (TFR) module includes forming a TFR element over a substrate; annealing the TFR element to reduce the temperature coefficient of resistance (TCR) of the TFR element; and after forming and annealing the TFR element, forming a pair of conductive TFR heads in contact with the TFR element. By forming the TFR element before the TFR heads, the TFR element may be annealed without affecting the TFR heads, and thus may be formed from various materials with different annealing properties, e.g., SiCCr and SiCr. Thus, the TFR element may be annealed to achieve a near 0 ppm TCR, without affecting the later-formed TFR heads. The TFR module may be formed using a damascene CMP approach and using only a single added mask layer. Further, vertically-extending “ridges” at edges of the TFR element may be removed or eliminated to further improve the TCR performance.

公开(公告)号：US10896888B2

公开(公告)日：2021-01-19

申请号：US16157826

申请日：2018-10-11

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Andrew Taylor

IPC: H01L23/10 ,  H01L23/00 ,  H01L21/768

Abstract: An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

公开(公告)号：US20190287936A1

公开(公告)日：2019-09-19

申请号：US16157826

申请日：2018-10-11

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Andrew Taylor

IPC: H01L23/00 ,  H01L23/10 ,  H01L21/768

Abstract: An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

公开(公告)号：US20190096751A1

公开(公告)日：2019-03-28

申请号：US16103538

申请日：2018-08-14

Applicant: Microchip Technology Incorporated

Inventor： Justin Hiroki Sato ,  Bonnie Hamlin ,  Andrew Taylor ,  Bomy Chen ,  Brian Hennes

IPC: H01L21/768

Abstract: A method of forming interconnects in a semiconductor device is provided. A mask including first and second openings is formed over a non-conductive structure. An etch is performed through the mask openings to define (a) a via trench having a via trench width and (b) an interconnect trench having a smaller width than the via trench width. A fill layer is deposited over the structure and (a) fills only a partial width of the via trench to thereby define via trench cavity and (b) fills the full width of the interconnect trench. A further etch is performed through the via trench cavity to form a via opening extending downwardly from the via trench. The remaining fill layer material is removed. The interconnect trench, via trench, and via opening are metallized to form a trench interconnect, a via interconnect, and a via extending downwardly from the via interconnect.