公开(公告)号：US12132016B2

公开(公告)日：2024-10-29

申请号：US18446028

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Yu Tsai ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/03013 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0355 ,  H01L2224/03612 ,  H01L2224/03622 ,  H01L2224/0381 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05546 ,  H01L2224/05564 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/2781 ,  H01L2224/27831 ,  H01L2224/29006 ,  H01L2224/29027 ,  H01L2224/29028 ,  H01L2224/32145 ,  H01L2224/32225

摘要： A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

公开(公告)号：US20240274554A1

公开(公告)日：2024-08-15

申请号：US18632532

申请日：2024-04-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TENG-YEN HUANG

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L24/02 ,  H01L2224/02372 ,  H01L2224/03001 ,  H01L2224/03011 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05193 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80379 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/0504 ,  H01L2924/0509 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2924/30105

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

公开(公告)号：US20230361062A1

公开(公告)日：2023-11-09

申请号：US17738016

申请日：2022-05-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Huan Fu ,  Ying-Tsung Chen ,  Jiun-Jie Huang ,  Wen-Han Hung ,  Jen-Pan Wang

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/0345 ,  H01L2224/03622 ,  H01L2224/03466 ,  H01L2224/0346 ,  H01L2224/03452 ,  H01L2224/05018 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/0401 ,  H01L2224/05559 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2924/0496 ,  H01L2924/0132 ,  H01L2224/13113 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/014 ,  H01L2224/13082 ,  H01L24/13 ,  H01L2224/05564 ,  H01L2924/20107 ,  H01L2924/20108

摘要： A semiconductor device includes a device layer, a first passivation layer, an aluminum pad, a second passivation layer, an under-ball metallurgy (UBM) pad and a connector. The device layer is disposed over a substrate, wherein the device layer includes a top metal feature. The first passivation layer is disposed over the device layer. The aluminum pad penetrates through the first passivation layer and is electrically connected to the top metal feature. The second passivation layer is disposed over the aluminum pad. The UBM pad penetrates through the second passivation layer and is electrically connected to the aluminum pad. The connector is disposed over the UBM pad. In some embodiments, a first included angle between a sidewall and a bottom of the aluminum pad is greater than a second included angle between a sidewall and a bottom of the UBM pad.

公开(公告)号：US20230360946A1

公开(公告)日：2023-11-09

申请号：US17738182

申请日：2022-05-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hsin YANG ,  Dian-Hau CHEN ,  Yen-Ming CHEN

IPC分类号： H01L21/683 ,  H01L23/00

CPC分类号： H01L21/6835 ,  H01L24/80 ,  H01L24/05 ,  H01L24/08 ,  H01L24/03 ,  H01L2221/68381 ,  H01L2224/80006 ,  H01L2224/80379 ,  H01L2224/808 ,  H01L2224/03622 ,  H01L2224/0346 ,  H01L2224/03845 ,  H01L2224/05647 ,  H01L2224/05657 ,  H01L2224/05655 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/05666 ,  H01L2224/08145 ,  H01L28/87

摘要： A method for forming a semiconductor structure is provided. The method includes forming a contact feature over an insulating layer, forming a first passivation layer over the contact feature, and etching the first passivation layer to form a trench exposing the contact feature. The method also includes forming an oxide layer over the contact feature and the first passivation layer and in the trench, forming a first non-conductive structure over the oxide layer, and patterning the first non-conductive structure to form a gap. The method further includes filling a conductive material in the gap to form a first conductive feature. The first non-conductive structure and the first conductive feature form a first bonding structure. The method further includes attaching a carrier substrate to the first bonding structure via a second bonding structure over the carrier substrate.

公开(公告)号：US20230238341A1

公开(公告)日：2023-07-27

申请号：US18079610

申请日：2022-12-12

申请人： STMicroelectronics Pte Ltd

发明人： Churn Weng YIM ,  Maurizio Gabriele CASTORINA ,  Voon Cheng NGWAN ,  Yean Ching YONG ,  Ditto ADNAN ,  Fadhillawati TAHIR

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/05073 ,  H01L2224/05573 ,  H01L2224/022 ,  H01L2224/0219 ,  H01L2224/03019 ,  H01L2224/03466 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05647

摘要： A bonding pad for an integrated circuit is formed by a stack of bonding pad layers. A lower bonding pad layer is supported by a bonding pad support layer. A passivation layer extends over the lower bonding pad layer and includes a passivation opening at a portion of an upper surface of the lower bonding pad layer. An upper bonding pad layer rests on said passivation layer and in the passivation opening in contact with the lower bonding pad layer.

公开(公告)号：US10083925B2

公开(公告)日：2018-09-25

申请号：US15836370

申请日：2017-12-08

申请人： Delta Electronics Int'l (Singapore) Pte Ltd

发明人： Qin-Jia Cai ,  Da-Jung Chen

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/03 ,  H01L21/4846 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02317 ,  H01L2224/0361 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0381 ,  H01L2224/04105 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2924/19105

摘要： A packaging process of an electronic component includes the following steps. Firstly, a semi-package unit is provided. The semi-package unit includes a first insulation layer and an electronic component. The electronic component is partially embedded within the first insulation layer. The electronic component includes at least one conducting terminal. Then, a metal layer is formed over the surface of the semi-package unit and a part of the metal layer is removed, so that a metal mask is formed on the surface of the semi-package unit and the at least one conducting terminals is exposed. Then, a metal re-distribution layer is formed on the metal mask and the at least one conducting terminal. Then, a part of the metal re-distribution layer and a part of the metal mask are removed, so that at least one contact pad corresponding to the at least one conducting terminal is produced.

公开(公告)号：US09865555B2

公开(公告)日：2018-01-09

申请号：US15454230

申请日：2017-03-09

申请人： Texas Instruments Incorporated

发明人： Manoj K. Jain

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L23/528

CPC分类号： H01L24/05 ,  H01L23/528 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/81815 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

摘要： An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

公开(公告)号：US20170236792A1

公开(公告)日：2017-08-17

申请号：US15429198

申请日：2017-02-10

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Fook Hong LEE ,  Juan Boon TAN ,  Ee Jan KHOR

IPC分类号： H01L23/00 ,  G03F1/36 ,  G06F17/50

CPC分类号： H01L24/03 ,  G03F1/36 ,  G06F17/5072 ,  G06F17/5081 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/02 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/01013

摘要： Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

公开(公告)号：US09679862B2

公开(公告)日：2017-06-13

申请号：US14555959

申请日：2014-11-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Yen-Liang Lin ,  Tin-Hao Kuo ,  Sheng-Yu Wu ,  Chen-Shien Chen

IPC分类号： H01L23/49 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L24/17 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/11462 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17132 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a semiconductor chip. The semiconductor chip includes a surface facing the plurality of conductive traces and a plurality of conductive pads on the surface and correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof.

公开(公告)号：US20170162541A1

公开(公告)日：2017-06-08

申请号：US15437193

申请日：2017-02-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Feng Chen ,  Kai-Chiang Wu ,  Chun-Lin Lu ,  Hung-Jui Ko

IPC分类号： H01L23/00 ,  H01L21/78 ,  H01L23/544

CPC分类号： H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/10 ,  H01L23/147 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/6024 ,  H01L2223/5446 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11318 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.