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    Methods of exposing conductive Vias of semiconductor devices and related semiconductor devices
    1.
    发明授权
    Methods of exposing conductive Vias of semiconductor devices and related semiconductor devices 有权

    公开(公告)号：US12237217B2

    公开(公告)日：2025-02-25

    申请号：US17188734

    申请日：2021-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Hongqi Li ,  Anurag Jindal ,  Irina Vasilyeva

    IPC: H01L21/768 ,  H01L23/48 ,  H01L23/538

    Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

    CONDUCTIVE INTERCONNECT STRUCTURES INCORPORATING NEGATIVE THERMAL EXPANSION MATERIALS AND ASSOCIATED SYSTMES, DEVICES, AND METHODS
    4.
    发明申请
    CONDUCTIVE INTERCONNECT STRUCTURES INCORPORATING NEGATIVE THERMAL EXPANSION MATERIALS AND ASSOCIATED SYSTMES, DEVICES, AND METHODS 有权
    包含负离子热膨胀材料的导电互连结构和相关的综合，装置和方法

    公开(公告)号：US20150340282A1

    公开(公告)日：2015-11-26

    申请号：US14815560

    申请日：2015-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Shyam Ramalingam

    IPC: H01L21/768 ,  H01L21/288

    CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

    Abstract translation: 本文公开了具有并入负扩张（NTE）材料的互连的半导体器件。 在一个实施例中，半导体器件包括具有至少部分延伸穿过衬底的开口的衬底。 具有正的热膨胀系数（CTE）的导电材料部分地填充开口。 具有负CTE的负热膨胀（NTE）也部分填充开口。 在一个实施例中，导电材料包括铜，NTE材料包括钨酸锆。

    METHODS OF EXPOSING CONDUCTIVE VIAS OF SEMICONDUCTOR DEVICES AND RELATED SEMICONDUCTOR DEVICES
    6.
    发明申请
    METHODS OF EXPOSING CONDUCTIVE VIAS OF SEMICONDUCTOR DEVICES AND RELATED SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210183697A1

    公开(公告)日：2021-06-17

    申请号：US17188734

    申请日：2021-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Hongqi Li ,  Anurag Jindal ,  Irina Vasilyeva

    IPC: H01L21/768 ,  H01L23/538 ,  H01L23/48

    Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

    Devices, systems and methods for manufacturing through-substrate vias and front-side structures
    9.
    发明授权
    Devices, systems and methods for manufacturing through-substrate vias and front-side structures 有权
    用于制造贯穿基板通孔和前端结构的装置，系统和方法

    公开(公告)号：US09305865B2

    公开(公告)日：2016-04-05

    申请号：US14068837

    申请日：2013-10-31

    Applicant: Micron Technology, Inc.

    Inventor： Anurag Jindal ,  Jian He ,  Lalapet Rangan Vasudevan ,  Kyle K. Kirby ,  Hongqi Li

    IPC: H01L21/00 ,  H01L21/76 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

    Abstract translation: 制造具有贯通衬底通孔（TSV）的半导体器件和半导体器件的方法。 制造半导体器件的方法的一个实施例包括通过电介质结构和半导体衬底的至少一部分形成开口，以及形成具有衬在开口上的第一部分的电介质衬垫材料和在外表面上的第二部分 电介质结构横向于开口外侧。 该方法还包括去除导电材料，使得电介质衬垫材料的第二部分被暴露，并且在电耦合到TSV的电介质衬垫材料的第二部分中形成镶嵌导电线。

    DEVICES, SYSTEMS, AND METHODS RELATED TO PLANARIZING SEMICONDUCTOR DEVICES AFTER FORMING OPENINGS
    10.
    发明申请
    DEVICES, SYSTEMS, AND METHODS RELATED TO PLANARIZING SEMICONDUCTOR DEVICES AFTER FORMING OPENINGS 审中-公开
    在形成开口之后平面化半导体器件的器件，系统和方法

    公开(公告)号：US20150206801A1

    公开(公告)日：2015-07-23

    申请号：US14607647

    申请日：2015-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Wayne H. Huang ,  Anurag Jindal

    IPC: H01L21/768 ,  H01L21/02 ,  H01L21/304 ,  H01L21/321

    CPC classification number: H01L21/76898 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/304 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/743 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76883

    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and a dielectric liner including dielectric material along sidewalls of openings, e.g., through-substrate openings, of the semiconductor device and excess dielectric material outside the openings. The method further includes forming a metal layer including metal plugs within the openings and excess metal. The excess metal and the excess dielectric material are simultaneously chemically-mechanically removed using a slurry including ceria and ammonium persulfate. The slurry is selected to cause selectivity for removing the excess dielectric material relative to the stop layer greater than about 5:1 as well as selectivity for removing the excess dielectric material relative to the excess metal from about 0.5:1 to about 1.5:1.

    Abstract translation: 本文公开了制造半导体器件的方法。 根据特定实施例配置的方法包括形成包含电介质材料的阻挡层和电介质衬垫，所述阻挡层和电介质衬垫沿着半导体器件的开口的侧壁（例如贯穿衬底开口）和开口外的多余电介质材料。 该方法还包括在开口内形成包括金属塞的金属层和多余的金属。 使用包括二氧化铈和过硫酸铵的浆料同时化学机械地除去多余的金属和过量的电介质材料。 选择浆料以引起相对于止挡层去除多余电介质材料的选择性大于约5:1，以及相对于多余金属从约0.5:1至约1.5:1去除多余电介质材料的选择性。

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