公开(公告)号：US20220278113A1

公开(公告)日：2022-09-01

申请号：US17746671

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Gianpietro Carnevale

IPC: H01L27/1157 ,  G11C16/08 ,  H01L27/11582 ,  G06F3/06 ,  H01L27/11573 ,  G11C8/14

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10790303B2

公开(公告)日：2020-09-29

申请号：US16793560

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Woohee Kim ,  John D. Hopkins ,  Changhan Kim

IPC: H01L21/28 ,  H01L21/02 ,  H01L27/11582 ,  H01L29/10 ,  H01L27/1157 ,  H01L29/423

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels include conductive wordline material having terminal ends. Charge blocking material is along the terminal ends of the conductive wordline material and has first vertical faces. The insulative levels have terminal ends with second vertical faces. The second vertical faces are laterally offset relative to the first vertical faces. Charge-trapping material is along the first vertical faces, and extends partially along the second vertical faces. The charge-trapping material is configured as segments which are vertically spaced from one another by gaps. Charge-tunneling material extends along the segments of the charge-trapping material. Channel material extends vertically along the stack, and is spaced from the charge-trapping material by the charge-tunneling material. The channel material extends into the gaps. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11362103B2

公开(公告)日：2022-06-14

申请号：US16987187

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Gianpietro Carnevale

IPC: H01L27/1157 ,  G11C16/08 ,  H01L27/11582 ,  G06F3/06 ,  H01L27/11573 ,  G11C8/14

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210167089A1

公开(公告)日：2021-06-03

申请号：US17177357

申请日：2021-02-17

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Richard J. Hill ,  John D. Hopkins ,  Collin Howder

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11524

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.

公开(公告)号：US11832447B2

公开(公告)日：2023-11-28

申请号：US17746671

申请日：2022-05-17

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Gianpietro Carnevale

IPC: H01L27/1157 ,  H10B43/35 ,  G11C16/08 ,  G06F3/06 ,  G11C8/14 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  G06F3/0688 ,  G11C8/14 ,  G11C16/08 ,  H10B43/27 ,  H10B43/40

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230041396A1

公开(公告)日：2023-02-09

申请号：US17973435

申请日：2022-10-25

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim

IPC: H01L27/1157 ,  H01L29/792 ,  H01L27/11565 ,  H01L29/66 ,  H01L29/51 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/11578 ,  H01L27/11524

Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

公开(公告)号：US11527550B2

公开(公告)日：2022-12-13

申请号：US17177357

申请日：2021-02-17

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Richard J. Hill ,  John D. Hopkins ,  Collin Howder

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L21/28

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.

公开(公告)号：US20220199645A1

公开(公告)日：2022-06-23

申请号：US17692004

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Chet E. Carter ,  Cole Smith ,  Collin Howder ,  Richard J. Hill ,  Jie Li

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66 ,  H01L29/10 ,  H01L21/28 ,  H01L27/11529 ,  H01L27/1157

Abstract: Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

公开(公告)号：US10937798B2

公开(公告)日：2021-03-02

申请号：US16179572

申请日：2018-11-02

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Richard J. Hill ,  John D. Hopkins ,  Collin Howder

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L21/28

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.

公开(公告)号：US10903221B2

公开(公告)日：2021-01-26

申请号：US15855089

申请日：2017-12-27

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/11565 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L27/11578 ,  H01L27/11524

Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).