公开(公告)号：US09263095B2

公开(公告)日：2016-02-16

申请号：US13953495

申请日：2013-07-29

Applicant: Micron Technology, Inc.

Inventor： Kunal Parekh ,  David Hwang ,  Wen Kuei Huang ,  Kuo Chen Wang ,  Ching Kai Lin

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/405 ,  H01L29/66 ,  H01L29/78 ,  G11C5/02 ,  H01L27/105

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C11/405 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10879 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.

公开(公告)号：US20130309839A1

公开(公告)日：2013-11-21

申请号：US13951793

申请日：2013-07-26

Applicant: Micron Technology, Inc.

Inventor： Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L29/66795 ,  H01L29/7853

Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract translation: Fin-FET（鳍场效应晶体管）器件和制造方法被公开。 鳍式FET器件包括可在源极区域和漏极区域之间形成沟道区域的双鳍结构。 在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在一对STI结构之间限定衬底的一部分中的凹部，以及凹陷 所述一对STI结构使得所得到的双翅片结构从所述基板的有效表面突出。 双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。 还公开了包括这种鳍式FET器件的电子系统。

公开(公告)号：US09219001B2

公开(公告)日：2015-12-22

申请号：US13951793

申请日：2013-07-26

Applicant: Micron Technology, Inc.

Inventor： Aaron R. Wilson ,  Larson Lindholm ,  David Hwang

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L29/66795 ,  H01L29/7853

Abstract: Fin-FET (fin field-effect transistor) devices and methods of fabrication are disclosed. The fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of a substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structures protrude from an active surface of the substrate. The dual fin structures may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract translation: Fin-FET（鳍场效应晶体管）器件和制造方法被公开。 鳍式FET器件包括可在源极区域和漏极区域之间形成沟道区域的双鳍结构。 在一些实施例中，通过形成浅沟槽隔离结构，使用一对浅沟槽隔离（STI）结构作为掩模来形成双鳍结构，以在一对STI结构之间限定衬底的一部分中的凹部，以及凹陷 所述一对STI结构使得所得到的双翅片结构从所述基板的有效表面突出。 双鳍结构可用于形成单栅极，双栅极或三栅极鳍FET器件。 还公开了包括这种鳍式FET器件的电子系统。

公开(公告)号：US20140231894A1

公开(公告)日：2014-08-21

申请号：US14265928

申请日：2014-04-30

Applicant: Micron Technology, Inc.

Inventor： Kunal Parekh ,  Ceredig Roberts ,  Thy Tran ,  Jim Jozwiak ,  David Hwang

IPC: H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10885

Abstract: A method is disclosed for forming a memory device having buried access lines (e.g., wordlines) and buried data/sense lines (e.g., digitlines) disposed below vertical cell contacts. The buried wordlines may be formed trenches in a substrate extending in a first direction, and the buried digitlines may be formed from trenches in a substrate extending in a second direction perpendicular to the first direction. The buried digitlines may be coupled to a silicon sidewall by a digitline contact disposed between the digitlines and the silicon substrate.

Abstract translation: 公开了一种用于形成具有埋设的访问线（例如字线）和布置在垂直单元触点下方的掩埋数据/感测线（例如，数字线）的存储器件的方法。 掩埋字线可以在沿第一方向延伸的衬底中形成沟槽，并且掩埋的数字线可以由垂直于第一方向的第二方向延伸的衬底中的沟槽形成。 埋置的数字线可以通过设置在数字线和硅衬底之间的数字线接触件耦合到硅侧壁。

公开(公告)号：US20130314967A1

公开(公告)日：2013-11-28

申请号：US13953495

申请日：2013-07-29

Applicant: Micron Technology, Inc.

Inventor： Kunal Parekh ,  David Hwang ,  Wen Kuei Huang ,  Kuo Chen Wang ,  Ching Kai Lin

IPC: G11C5/06 ,  H01L27/105 ,  G11C5/02

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C11/405 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10879 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a word line formed in a second horizontal planar volume above the first horizontal planar volume and storage devices formed on top of the vertical access devices, such as finFETs, in a third horizontal planar volume above the second horizontal planar volume. The memory array may have a 4F2 architecture, wherein each memory cell includes two vertical access devices, each coupled to a single storage device.

Abstract translation: 具有存储单元的存储器阵列及其形成方法。 存储器阵列可以具有形成在第一水平平面体积中的掩埋数字线，形成在第一水平平面体积上方的第二水平平面体积中的字线和形成在垂直存取装置（例如finFET）的顶部上的存储装置， 在第二水平平面体积之上的第三水平平面体积。 存储器阵列可以具有4F2架构，其中每个存储器单元包括两个垂直存取设备，每个垂直存取设备耦合到单个存储设备。