公开(公告)号：US20240249758A1

公开(公告)日：2024-07-25

申请号：US18623355

申请日：2024-04-01

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US11238909B2

公开(公告)日：2022-02-01

申请号：US16541097

申请日：2019-08-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Elancheren Durai ,  Quincy R. Holton

IPC: G11C7/22 ,  G11C8/12 ,  G06F13/16 ,  G11C11/4074 ,  G06F13/20 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4093

Abstract: Apparatuses and methods for setting operational parameters of a memory based on location are disclosed. The operational parameters may include operational parameters for an input/output circuit. For example, operational parameters may be for output driver circuit impedance, equalization for input receiver circuits, termination impedance, as well as others. Location information is provided to a memory device and used for setting the operational parameter. A nominal operational parameter setting may be offset based on the location information, thereby tailoring the operational parameter of the memory device according to location in some examples. The location information may be memory slot address for location based on memory module location. The location information may be related to a location of a memory device within a sub-system. The location information may be provided to unused terminals of a memory device, for example, unused data terminals in some examples.

公开(公告)号：US11948661B2

公开(公告)日：2024-04-02

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US20240020018A1

公开(公告)日：2024-01-18

申请号：US17865203

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： William C. Filipiak ,  Elancheren Durai ,  Quincy R. Holton ,  Adam Satar ,  Brett Hunter ,  David R. Silwanowicz

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

公开(公告)号：US11416250B2

公开(公告)日：2022-08-16

申请号：US16415742

申请日：2019-05-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Elancheren Durai

IPC: G11C19/28 ,  G11C11/16 ,  G06F9/30

Abstract: In some embodiments, a programmable circuit configured to store a shift setting for a mode register parameter, and a shift circuit is configured to receive a first value of a mode register parameter. In response to the shift setting signal having a first value, the shift circuit is configured to adjust the first value of the mode register parameter to provide the mode register parameter having a second value. In response to the shift setting signal having a second value, the shift circuit is further configured to provide the first value of the mode register parameter as the second value of the mode register parameter. Circuitry coupled to an input/output terminal is configured to set a configuration based on the second value of the mode register parameter. The mode register parameter includes an on-die termination (ODT) parameter and the circuitry includes an ODT circuit, in some examples.

公开(公告)号：US20240281151A1

公开(公告)日：2024-08-22

申请号：US18651032

申请日：2024-04-30

Applicant: Micron Technology, Inc.

Inventor： William C. Filipiak ,  Elancheren Durai ,  Quincy R. Holton ,  Adam Satar ,  Brett Hunter ,  David R. Silwanowicz

IPC: G06F3/06 ,  G11C7/04 ,  G11C11/406 ,  G11C16/34

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C11/40626 ,  G11C16/3418

Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

公开(公告)号：US12001686B2

公开(公告)日：2024-06-04

申请号：US17865203

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： William C. Filipiak ,  Elancheren Durai ,  Quincy R. Holton ,  Adam Satar ,  Brett Hunter ,  David R. Silwanowicz

IPC: G06F1/00 ,  G06F3/06 ,  G11C7/04 ,  G11C11/406 ,  G11C16/34

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C11/40626 ,  G11C16/3418

Abstract: Methods, apparatuses and systems related to managing deck-specific read levels are described. The apparatus may include a memory array having the memory cells organized into two or more decks. The apparatus can determine a delay between programming the decks. The apparatus can derive and implement the deck-specific read levels by selectively adjusting a base read level with an offset level according to the delay and/or the targeted read location.

公开(公告)号：US20220391210A1

公开(公告)日：2022-12-08

申请号：US17889210

申请日：2022-08-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Elancheren Durai

IPC: G06F9/30 ,  G11C19/28

Abstract: In some embodiments, a programmable circuit configured to store a shift setting for a mode register parameter, and a shift circuit is configured to receive a first value of a mode register parameter. In response to the shift setting signal having a first value, the shift circuit is configured to adjust the first value of the mode register parameter to provide the mode register parameter having a second value. In response to the shift setting signal having a second value, the shift circuit is further configured to provide the first value of the mode register parameter as the second value of the mode register parameter. Circuitry coupled to an input/output terminal is configured to set a configuration based on the second value of the mode register parameter. The mode register parameter includes an on-die termination (ODT) parameter and the circuitry includes an ODT circuit, in some examples.

公开(公告)号：US20210383849A1

公开(公告)日：2021-12-09

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C8/12 ,  G11C8/06 ,  G11C7/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US11030141B2

公开(公告)日：2021-06-08

申请号：US16737182

申请日：2020-01-08

Applicant: Micron Technology, Inc.

Inventor： Elancheren Durai

IPC: G11C11/34 ,  G06F13/40 ,  G11C11/40 ,  G11C7/10 ,  G11C7/22

Abstract: An apparatus may include at least one output circuit configured to generate a desired output driver impedance (ODI) during a first operational mode. The least one output circuit may further be configured to independently generate a desired on-die termination (ODT) impedance during a second operational mode. Memory systems, memory devices, electronic systems, and related methods of operation are also described.