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公开(公告)号：US12235722B2
公开(公告)日：2025-02-25
申请号：US18216160
申请日：2023-06-29
Applicant: Micron Technology, Inc.
Inventor： Paolo Amato , Daniele Balluchi , Danilo Caraccio , Emanuele Confalonieri , Marco Sforzin
IPC: G06F11/10
Abstract: A channel width can depend on a quantity of memory units (e.g., memory dice) that forms a channel as well as a size of the memory units. A memory system can operate with memory units configured to exchange (e.g., transfer to and/or from) data at a rate of smaller granularity that can provide more various options for channel widths, which can further allow a fine-tuned optimization of the memory system in association with its bandwidth and latency in transferring data from and/or to the memory units. The channels whose channel width is fine-tuned with such memory units can be further used to provide a reliability, availability, and serviceability (RAS) protection, such as a redundant array of independent disks (RAID) protection.
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公开(公告)号：US12222806B2
公开(公告)日：2025-02-11
申请号：US18215588
申请日：2023-06-28
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato
IPC: G06F11/10 , G06F3/06 , G06F12/0868 , H04L67/568
Abstract: Data protection with error correction/detection capabilities can be provided on a cache line basis. When provided on a cache line basis to collectively protect the cache line data, the error correction/detection capabilities can be provided with fewer number of bits (e.g., error correction code (ECC) and/or cyclic redundancy check (CRC) bits) as compared to providing the same error correction/detection capabilities individually on a subset of the cache line data.
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公开(公告)号：US20250046369A1
公开(公告)日：2025-02-06
申请号：US18924813
申请日：2024-10-23
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Luca Barletta , Marco Pietro Ferrari , Antonino Favano
IPC: G11C11/56 , G11C11/4074 , G11C11/4099
Abstract: Systems, methods, and apparatuses are provided for drift compensation for codewords in memory. A memory device comprises memory cells and circuitry configured to sense a codeword stored in the array of memory cells using a reference voltage and determine an amount by which to adjust the reference voltage used to sense the codeword based on an estimated weight of the original codeword, a mean of threshold voltage values of each memory cell of the sensed codeword, and a total quantity of memory cells of the sensed codeword. The circuitry can further be configured to adjust the reference voltage used to sense the codeword by the determined amount.
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公开(公告)号：US12210413B2
公开(公告)日：2025-01-28
申请号：US18211881
申请日：2023-06-20
Applicant: Micron Technology, Inc.
Inventor： Joseph M. McCrate , Marco Sforzin , Paolo Amato , Lingming Yang , Nevil N. Gajera
Abstract: Methods, systems, and devices for data correction schemes with reduced device overhead are described. A memory system may include a set of memory devices storing data and check codes associated with the data. The memory system may additionally include a single parity device storing parity information associated with the data. During a read operation of a set of data, a controller of the memory system may detect an error in data associated with a first check code, the data including two or more subsets of the set of data received from two or more corresponding memory devices. The controller may generate candidate data corresponding to one of the two or more subsets using the parity information and remaining subsets of the set of data. Then the controller may determine whether the candidate data is correct by comparing the first check code with a check value generated using the candidate data.
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公开(公告)号：US20240429944A1
公开(公告)日：2024-12-26
申请号：US18813896
申请日：2024-08-23
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Yang Lu
Abstract: Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.
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Patent Agency Ranking
公开(公告)号：US20240428833A1
公开(公告)日：2024-12-26
申请号：US18827484
申请日：2024-09-06
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Luca Barletta , Marco Pietro Ferrari , Antonino Favano
Abstract: Systems, methods, and apparatuses are provided for drift compensation for codewords in memory. A memory device comprises memory cells and circuitry configured to sense a codeword stored in the memory cells. The circuitry is further configured to determine a value of a cell metric of each memory cell of the sensed codeword, wherein the value of the cell metric of each of the memory cells is determined based on a summation of a threshold voltage value of each of the memory cells, a mean of the threshold voltage values of the memory cells, and a value proportional to the mean of the threshold voltage values of the memory cells. The circuitry is further configured to determine which cell metric of each of the memory cells has a lowest value, input that cell metric into a Pearson detector, and determine the originally programmed data of the codeword using the Pearson detector.
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公开(公告)号：US20240411644A1
公开(公告)日：2024-12-12
申请号：US18813785
申请日：2024-08-23
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Joseph M. McCrate
IPC: G06F11/10
Abstract: A redundant array of independent disks (RAID) protection can be provided along with other types of error correction code (ECC) schemes that correct either errors in data prior to the data being input to the RAID process or residual errors from the RAID process. The ECC schemes can utilize parity bits generated using a parity matrix whose bit patterns have an amount of bits that can be used to identify a location of the memory system from which data corresponding to the respective bit pattern is read.
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公开(公告)号：US20240411451A1
公开(公告)日：2024-12-12
申请号：US18808341
申请日：2024-08-19
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Daniele Balluchi
Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.
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公开(公告)号：US20240370186A1
公开(公告)日：2024-11-07
申请号：US18772553
申请日：2024-07-15
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Christophe Vincent Antoine Laurent , Riccardo Muzzetto
IPC: G06F3/06
Abstract: The present disclosure relates to providing multiple error correction code protection levels in memory. One device includes an array of memory cells and an operating circuit for managing operation of the array. The operating circuit comprises an encoding unit configured to generate a codeword for a first error correction code (ECC) protection level and a second ECC protection level, and decoding unit configured to perform an ECC operation on the codeword at the first ECC protection level and the second ECC protection level. The codeword comprises payload data stored in a plurality of memory cells of the array, and parity data associated with the payload data stored in parity cells of the array.
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公开(公告)号：US12087391B2
公开(公告)日：2024-09-10
申请号：US17948423
申请日：2022-09-20
Applicant: Micron Technology, Inc.
Inventor： Marco Sforzin , Paolo Amato , Luca Barletta , Marco Pietro Ferrari , Antonino Favano
CPC classification number: G11C7/1063 , G11C7/1057 , G11C7/1069 , G11C11/5621
Abstract: Systems, methods, and apparatuses are provided for drift compensation for codewords in memory. A memory device comprises memory cells and circuitry configured to sense a codeword stored in the memory cells. The circuitry is further configured to determine a value of a cell metric of each memory cell of the sensed codeword, wherein the value of the cell metric of each of the memory cells is determined based on a summation of a threshold voltage value of each of the memory cells, a mean of the threshold voltage values of the memory cells, and a value proportional to the mean of the threshold voltage values of the memory cells. The circuitry is further configured to determine which cell metric of each of the memory cells has a lowest value, input that cell metric into a Pearson detector, and determine the originally programmed data of the codeword using the Pearson detector.
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