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    Time to digital circuitry with error protection scheme
    1.
    发明授权
    Time to digital circuitry with error protection scheme 有权

    公开(公告)号：US11742868B1

    公开(公告)日：2023-08-29

    申请号：US17677724

    申请日：2022-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Eric A. Becker ,  Tyler J. Gomm

    IPC: H03M1/06 ,  G04F10/00 ,  H03M7/16 ,  H03K3/03

    CPC classification number: H03M1/0617 ,  G04F10/005 ,  H03K3/0315 ,  H03M7/165

    Abstract: A time to digital circuit may provide a time measurement of an event, or a time measurement of a duration between multiple events. Various electronic devices may include one or more time to digital circuits. A time to digital circuit may include circuitry to use Thermometer Code for measuring the duration of the time. For example, the time to digital circuit may generate alternating signals using a ring oscillator when receiving an indication of an event. Moreover, the time to digital circuit may convert the alternating signals to a consistent signal with only one transition between high and low signals in multiple consecutive signals. Furthermore, the time to digital circuit may correct erroneous signal values of the consistent signals when multiple transitions between high and low signals in multiple consecutive signals occurs.

    ON-CHIP NOISE GENERATOR FOR POWER BUS
    2.
    发明公开
    ON-CHIP NOISE GENERATOR FOR POWER BUS 审中-公开

    公开(公告)号：US20230197138A1

    公开(公告)日：2023-06-22

    申请号：US17558512

    申请日：2021-12-21

    Applicant: Micron Technology, Inc.

    Inventor： Eric A. Becker ,  Tyler J. Gomm

    IPC: G11C11/4074 ,  G11C11/4076 ,  G06F7/58

    CPC classification number: G11C11/4074 ,  G11C11/4076 ,  G06F7/584 ,  G06F2207/581

    Abstract: An apparatus having a power bus supplying power to a component of a memory device. The apparatus includes a noise source circuit generating a plurality of noise source signals that simulate a real-world noise. The apparatus can include a pulse generator circuit that receives the noise source signal and outputs at least one noise profile signal based on the noise source signal. A bus shorting circuit can be connected to the pulse generator circuit to receive the at least one noise profile signal. The bus shorting circuit can have at least one transistor connected between a first rail and a second rail of the power bus. Based on the at least one noise profile signal, the bus shorting circuit intermittently connects the at least one transistor between the first rail to the second rail to induce noise on the power bus.

    TECHNIQUES FOR CLOCK SIGNAL JITTER GENERATION
    3.
    发明申请
    TECHNIQUES FOR CLOCK SIGNAL JITTER GENERATION 审中-公开

    公开(公告)号：US20190341096A1

    公开(公告)日：2019-11-07

    申请号：US16517230

    申请日：2019-07-19

    Applicant: Micron Technology, Inc.

    Inventor： Tyler J. Gomm

    IPC: G11C11/4076 ,  G06F7/58 ,  H03K5/13

    Abstract: A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signals, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.

    APPARATUSES AND METHODS FOR MAINTAINING A DUTY CYCLE ERROR COUNTER
    4.
    发明申请
    APPARATUSES AND METHODS FOR MAINTAINING A DUTY CYCLE ERROR COUNTER 审中-公开

    公开(公告)号：US20190214072A1

    公开(公告)日：2019-07-11

    申请号：US15868232

    申请日：2018-01-11

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yasuo Satoh ,  Tyler J. Gomm

    IPC: G11C11/4076 ,  H03K3/017 ,  G11C29/02 ,  H03K23/00 ,  H03M7/16

    CPC classification number: G11C11/4076 ,  G11C29/023 ,  H03K3/017 ,  H03K5/1565 ,  H03K19/21 ,  H03K23/005 ,  H03M7/16

    Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.

    Multiple device apparatus, systems, and methods
    5.
    发明授权
    Multiple device apparatus, systems, and methods 有权
    多设备装置，系统和方法

    公开(公告)号：US09123405B2

    公开(公告)日：2015-09-01

    申请号：US14099294

    申请日：2013-12-06

    Applicant: Micron Technology, Inc.

    Inventor： Tyler J. Gomm

    IPC: G11C8/18

    CPC classification number: G11C8/18

    Abstract: Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed.

    Abstract translation: 公开了用于在堆叠中的管芯中产生时钟信号并且在堆叠中的另一管芯中接收时钟信号的装置，系统和方法。 公开了附加装置，系统和方法。

    DELAY LINE OFF-STATE CONTROL WITH POWER REDUCTION
    6.
    发明申请
    DELAY LINE OFF-STATE CONTROL WITH POWER REDUCTION 有权
    延时线路断电控制

    公开(公告)号：US20140077852A1

    公开(公告)日：2014-03-20

    申请号：US14083875

    申请日：2013-11-19

    Applicant: Micron Technology, Inc.

    Inventor： Tyler J. Gomm ,  Debra Bell

    IPC: H03L7/08

    CPC classification number: H03L7/0802 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814

    Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.

    Abstract translation: 提供了一种用于控制用于实现功率降低的延迟线的方法和装置。 该装置包括延迟锁定环路，以基于参考信号和反馈信号之间的相位差来提供输出信号，所述延迟锁定环路包括至少一个延迟电路，该延迟电路包括多个逻辑门，该多个逻辑门被配置为提供基本均匀的降级 处于静态的多个NAND门。

    DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS
    8.
    发明申请
    DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS 有权
    延迟线，延迟信号的方法和延迟锁定

    公开(公告)号：US20130169335A1

    公开(公告)日：2013-07-04

    申请号：US13734745

    申请日：2013-01-04

    Applicant: Micron Technology, Inc.

    Inventor： Tyler J. Gomm

    IPC: H03K5/14

    CPC classification number: H03L7/0818 ,  H03K5/133 ,  H03K5/14 ,  H03L7/0814 ,  H03L7/089

    Abstract: Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.

    Abstract translation: 公开了锁定环路，延迟线路，延迟电路和用于延迟信号的方法。 示例延迟电路包括包括多个延迟级的延迟线，每个延迟级具有输入并且还具有单个反相延迟器件，并且还包括耦合到延迟线的两相出口树，并且被配置为提供第一和 第二输出时钟信号响应于来自多个延迟级的延迟级的输入的时钟信号。 另一示例延迟电路包括被配置为提供多个延迟的时钟信号的延迟线，每个延迟的时钟信号相对于等于单个反相延迟器件的延迟的先前延迟的时钟信号具有延迟。 示例延迟电路还包括被配置为响应延迟的时钟信号提供第一和第二输出时钟信号的两相出口树。

    Techniques for clock signal jitter generation
    10.
    发明授权
    Techniques for clock signal jitter generation 有权

    公开(公告)号：US10896719B2

    公开(公告)日：2021-01-19

    申请号：US16517230

    申请日：2019-07-19

    Applicant: Micron Technology, Inc.

    Inventor： Tyler J. Gomm

    IPC: G11C11/4076 ,  H03K5/13 ,  G06F7/58 ,  G11C7/22 ,  H03K5/00 ,  H03L7/08 ,  H03K23/54

    Abstract: A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signal, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.

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