公开(公告)号：US20230207488A1

公开(公告)日：2023-06-29

申请号：US17976409

申请日：2022-10-28

Applicant: Micron Technology, Inc.

Inventor： Faxing Che ,  Hong Wan Ng ,  Yeow Chon Ong ,  Wei Yu ,  Ling Pan ,  Lin Bu

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L25/50 ,  H01L25/0652 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2924/1438 ,  H01L2924/182 ,  H01L24/48 ,  H01L24/32 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48221 ,  H01L24/73 ,  H01L2224/73265 ,  H01L2224/73215 ,  H01L2224/48145 ,  H01L2224/32145 ,  H01L2224/32245

Abstract: A semiconductor package assembly includes a substrate, a die stack including at least a bottom die, an inert top spacer, and at least a first inert base spacer. The inert top and base spacers are exclusive of any circuits. A top surface of the inert top spacer is directly attached to a bottom surface of the bottom die in the die stack. A top surface of the first inert base spacer is directly attached to a bottom surface of the inert top spacer and a bottom surface of the first inert base spacer is directly attached to the substrate. The footprint of the inert base spacer is smaller than the footprint of the inert top spacer. In some embodiments, the footprint of the inert base spacer is positioned entirely within the footprint of the inert top spacer.

公开(公告)号：US20240047285A1

公开(公告)日：2024-02-08

申请号：US17883153

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Faxing Che ,  Wei Yu ,  Yeow Chon Ong ,  Shin Yueh Yang ,  Hong Wan Ng

IPC: H01L23/14 ,  H01L21/52

CPC classification number: H01L23/14 ,  H01L21/52

Abstract: A semiconductor device assembly includes a semiconductor die, a substrate, and a spacer directly coupled to the substrate. The spacer includes a flexible main body and a support structure embedded in the flexible main body, wherein the support structure has a higher stiffness than the flexible main body. The spacer carries the semiconductor die. The flexible main body of the spacer mitigates the effects of thermomechanical stress, for example caused by a mismatch between the coefficient of thermal expansion of the semiconductor die and the substrate. The embedded support structure provides strength needed to support the semiconductor die during assembly.

公开(公告)号：US20240039185A1

公开(公告)日：2024-02-01

申请号：US17815917

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Wei Yu ,  Ling Pan

IPC: H01R12/52 ,  H01R12/73 ,  H01R12/71

CPC classification number: H01R12/523 ,  H01R12/737 ,  H01R12/718

Abstract: Methods, systems, and devices for connection designs for memory systems are described. A memory system may include a package and a printed circuit board (PCB). An interface of the package may be coupled with the PCB via a set of springs, where each spring may include a material configured to deform based at least in part on a shape of the package, a shape of the PCB, or both. The memory system may also include a set of latches that may secure the package in a fixed position relative to the PCB. That is, the set of springs may provide an electrical connection between the package and the PCB, and the set of latches may provide a mechanical connection between the package and the PCB. In some examples, the package, the PCB, or both, may include one or more connection structures configured to receive the latches.

公开(公告)号：US20240071881A1

公开(公告)日：2024-02-29

申请号：US17894063

申请日：2022-08-23

Applicant: Micron Technology, Inc.

Inventor： Ling Pan ,  Wei Yu ,  Kelvin Tan Aik Boo

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/1403 ,  H01L2224/16227

Abstract: A semiconductor device assembly includes a semiconductor die and a substrate coupled to the semiconductor die. The substrate includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the second solder mask layer through the secondary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.